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path: root/llvm/test/CodeGen/RISCV/float-convert.ll
AgeCommit message (Expand)AuthorFilesLines
2025-11-26[RISCV] Remove intrinsic declarations in tests, NFC (#167474)Jianjian Guan1-8/+0
2025-09-24[RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352)Alex Bradbury1-28/+34
2025-08-27[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)Philip Reames1-8/+8
2025-08-14[RISCV] Improve instruction selection for most significant bit extraction (#1...Piotr Fusik1-17/+17
2025-07-21[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)Alex Bradbury1-22/+10
2025-06-27[DAG] canCreateUndefOrPoison - add handling for ISD::SELECT (#146046)Simon Pilgrim1-4/+4
2025-06-02[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w)...Alex Bradbury1-11/+11
2025-03-28[RISCV][MC] Enable printing of zext.b alias (#133502)Alex Bradbury1-2/+2
2025-02-13Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#12...Philip Reames1-18/+18
2025-02-12[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)Philip Reames1-18/+18
2024-11-15[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)Pengcheng Wang1-54/+54
2024-09-05[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)Craig Topper1-16/+16
2024-08-14[RISCV] Add signext attribute to return of fmv_x_w test in float-convert.ll. NFCCraig Topper1-5/+12
2024-08-08[RISCV] Add some Zfinx instructions to hasAllNBitUsers.Craig Topper1-5/+3
2024-04-29Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison ...Bjorn Pettersson1-79/+79
2024-04-29Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)...David Spickett1-79/+79
2024-04-26[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)Bjorn Pettersson1-79/+79
2024-04-15[mi-sched] Suppress register pressure with i64. (#88256)laichunfeng1-8/+8
2024-03-25[RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and isGuara...Craig Topper1-25/+23
2024-03-08[SelectionDAG] Allow FREEZE to be hoisted before FP SETCC. (#84358)Craig Topper1-40/+32
2024-03-07[RISCV] Insert a freeze before converting select to AND/OR. (#84232)Craig Topper1-112/+124
2024-01-07[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)Fangrui Song1-128/+128
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-18/+18
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-18/+18
2023-10-06[RISCV] Strip W suffix from ADDIW (#68425)Philip Reames1-9/+9
2023-05-03[RISCV][CodeGen] Support Zfinx codegenShao-Ce SUN1-0/+428
2023-04-29[TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT.Craig Topper1-97/+71
2023-03-27[RISCV] Move compressible registers to the beginning of the FP allocation order.Craig Topper1-61/+61
2023-03-16[RISCV]Optimize (riscvisd::select_cc x, 0, ne, x, 1)LiaoChunyu1-12/+6
2023-02-03[RISCV] Don't use constantpool for floating-point value if the value can be e...Han-Kuan Chen1-30/+30
2022-12-19[RISCV] Convert some tests to opaque pointers (NFC)Nikita Popov1-9/+9
2022-12-14[RISCV][CodeGen][SelectionDAG] Recursively check hasAllNBitUsers for logical ...Nitin John Raj1-5/+5
2022-12-01[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.Craig Topper1-2/+2
2022-11-25[RISCV] Use register allocation hints to improve use of compressed instructions.Craig Topper1-28/+28
2022-10-18[RISCV] Optimize SELECT_CC when the true value of select is ConstantLiaoChunyu1-110/+109
2022-10-13[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelectCraig Topper1-111/+84
2022-10-12[RISCV] Use branchless form for selects with 0 in either armPhilip Reames1-240/+203
2022-10-06[RISCV] Use branchless form for selects with -1 in either armPhilip Reames1-183/+133
2022-09-13[RISCV] Fix a bug in i32 FP_TO_UINT_SAT lowering on RV64.Craig Topper1-16/+38
2022-09-12[RISCV] Add test cases with result of fp_to_s/uint_sat sign/zero-extended fro...Craig Topper1-0/+189
2022-08-01[RISCV] Explicitly select second operand of branch condition to X0.Craig Topper1-120/+106
2022-06-06[RISCV] Use check-prefixes to reduce check linesShao-Ce SUN1-162/+75
2022-02-04[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.Craig Topper1-50/+30
2022-01-21[RISCV] Set CostPerUse to 1 iff RVC is enabledwangpc1-44/+44
2022-01-10[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK line...Craig Topper1-157/+102
2022-01-09[SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeN...Craig Topper1-24/+4
2022-01-08[RISCV] Add i8/i16 fptosi/fptoui and fptosi_sat/fptoui_sat tests. NFCCraig Topper1-0/+620
2022-01-08[RISCV] Add nounwind to remove some cfi directives from test CHECKs. NFCCraig Topper1-23/+3
2021-12-18[RISCV] Remove stale comments from tests. NFCCraig Topper1-2/+0
2021-11-22[RISCV] Reverse the order of loading/storing callee-saved registers.Hsiangkai Wang1-47/+47
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