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2026-02-12[WebAssembly] Error on Wasm SjLj if +exception-handling is missing (#181070)HEADmainHeejin Ahn6-10/+33
2026-02-12[AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe (#177334)Jonathan Thackray2-1915/+220
2026-02-12[AArch64][llvm] Preserve FP_TO_*_SAT VT operand in SVE scalar-combine (#177333)Jonathan Thackray2-0/+3299
2026-02-12[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)Matthew Devereau1-629/+648
2026-02-12[AArch64][GlobalISel] Add some extra sqxtn test coverage. NFCDavid Green2-20/+347
2026-02-12[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)Guy David1-0/+119
2026-02-12[AArch64][GlobalISel] Update and regnerate switch-cases-to-branch-and.ll. NFCDavid Green1-543/+438
2026-02-12[SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (#180727)Björn Pettersson13-44/+125
2026-02-12[DAGCombiner] Fix subvector extraction index for big-endian STLF (#180795)陈子昂2-2/+29
2026-02-12[AMDGPU] Add missing assert requirement to unit test (#181102)Lucas Ramirez1-0/+1
2026-02-12[AArch64][ISel] Add clmul to pmullb/t lowering (#180568)Matthew Devereau1-707/+1060
2026-02-12[SDAG] Copy flags in convertMask when legalizing vselect/setcc (#180979)David Green1-96/+12
2026-02-11[RISCV] Improve 2*XLEN SHL legalization with P extension. (#181056)Craig Topper2-33/+13
2026-02-11[RISCV] Use NSRL/NSRA for legalizing i64 shifts with P extension on RV32. (#1...Craig Topper1-38/+40
2026-02-12[Hexagon] Add support for V128i1/V64i1/V32i1 predicate store/load in HVX (#18...pkarveti1-0/+89
2026-02-12[AMDGPU][Scheduler] Fix inconsistent MI slots after rematerialization revert ...Lucas Ramirez1-0/+331
2026-02-11[AMDGPU][NFC] Fix test by removing debug flag in llvm.amdgcn.raw.buffer.atomi...Syadus Sefat1-1/+1
2026-02-11[RISC] Rename the P extensions srx/slx tests and add fshl/fshr intrinsic test...Craig Topper2-18/+414
2026-02-11[SPIRV] Scalarize single-element vectors in type creation (#180735)Dmitry Sidorov1-0/+53
2026-02-11[AMDGPU][ISel] `setcc` peephole for comparisons with upper 32 bits of a 64-bi...zGoldthorpe14-183/+394
2026-02-11[AMDGPU][GlobalIsel] Add register bank legalization rules for buffer atomic i...Syadus Sefat1-0/+282
2026-02-11[AMDGPU] Treat F64 TRANS instructions as VALU for S_DELAY_ALU insertion (#180...Jay Foad4-24/+37
2026-02-11AMDGPU/GlobalISel: RegBankLegalize for global atomic ordered add (#180829)vangthao951-2/+15
2026-02-11[AMDGPU] Add known bits for G_AMDGPU_COPY_SCC_VCC (#180560)vangthao9512-330/+81
2026-02-11[AArch64] Add extra fcmp+select tests. NFCDavid Green1-0/+522
2026-02-11[RISCV] improve `musttail` support (#170547)Folkert de Vries3-52/+592
2026-02-11[ExpandIRInsts] Support saturating fptoi (#179710)Nikita Popov1-1416/+469
2026-02-11[AArch64] Lower factor-of-2 interleaved stores to STNP (#177938)Tomer Shafir3-0/+2110
2026-02-11[AArch64] Avoid selecting XAR for reverse operations. (#178706)Ricardo Jesus2-3/+160
2026-02-11[RISCV][CodeGen] Combine vwaddu+vabd(u) to vwabda(u)Pengcheng Wang1-10/+14
2026-02-11[RISCV] Add precommit test for vwabda(u) combinePengcheng Wang1-0/+120
2026-02-11[RISCV] Add sp register as implicit/implicit-def register to save/restore cal...Jim Lin1-8/+8
2026-02-11[RISCV] Remove vp.reverse mask check in performVP_REVERSECombine (#180724)Luke Lau1-0/+15
2026-02-11[RISCV] Relax reversed mask's mask requirement in reverse to strided load/sto...Luke Lau2-9/+26
2026-02-11[Mips] Fix cttz.i32 fails to lower on mips16 (#179633)yingopq1-0/+61
2026-02-11[AArch64][ARM] Add some tests for fcmp or branches. NFCDavid Green2-0/+513
2026-02-11[AMDGPU] Introduce asyncmark/wait intrinsics (#180467)Sameer Sahasrabuddhe4-81/+520
2026-02-10[NewPM] Port x86-insert-x87-wait (#180128)Kyungtak Woo1-0/+4
2026-02-10[outliners] Turn nooutline into an Enum Attribute (#163665)Sam Elliott1-1/+1
2026-02-11[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12 (#180466)Sameer Sahasrabuddhe10-27/+644
2026-02-10[NewPM] Port x86-winehstate (#180687)Anshul Nigham6-0/+7
2026-02-11[AMDGPU] [GlobalIsel] Enabling lit tests for new regbank select (#180680)Abhinav Garg3-326/+598
2026-02-11[X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (#180472)woruyu1-0/+14
2026-02-10[AMDGPU] Fix LDS address correction in promoteConstantOffsetToImm for async s...Alexander Weinrauch2-0/+84
2026-02-10[DAGCombiner] Fix crash in reassociationCanBreakAddressingModePattern for mul...Alexander Weinrauch1-0/+52
2026-02-10[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension (#...Craig Topper2-0/+270
2026-02-10[SPIRV] Legalize extended integers for compare instructions. (#180254)Faijul Amin1-0/+34
2026-02-10[RISCV] Use ADDD for GPR Pair Move with P (#180671)Sam Elliott1-33/+51
2026-02-10[RISCV] Add (BSETI x0, 11) to isLoadImm for optimizeCondBranch (#180820)Craig Topper1-2/+60
2026-02-10AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomic cmpswap (#180666)vangthao954-8/+8
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