aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen
AgeCommit message (Expand)AuthorFilesLines
2025-12-09AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)HEADmainanjenner3-585/+140
2025-12-09[AArch64] recognise trn1/trn2 with flipped operands (#169858)Philip Ginsbach-Chen3-98/+152
2025-12-09[AMDGPU] Scavenge a VGPR to eliminate a frame index (#166979)Anshil Gandhi1-0/+469
2025-12-09[X86] fix typo: `MCVTTP2SIS` -> `MCVTTP2UIS` (#171229)Folkert de Vries1-6/+6
2025-12-09[X86] bitcnt-big-integer.ll - add additional test coverage where the source v...Simon Pilgrim1-0/+1612
2025-12-09[SPIRV] Start adding support for `int128` (#170798)Alex Voicu4-0/+122
2025-12-09[x86][AVX-VNNI] Fix VPDPWXXD Argument Types (#169456)BaiXilin12-156/+517
2025-12-09[NVPTX] Add IR pass for FMA transformation in the llc pipeline (#154735)Rajat Bajpai1-0/+247
2025-12-09[RISCV] Add VMNoV0 register class with only the VMaskVTs. (#171231)Craig Topper8-23/+23
2025-12-09[AArch64] Make the list of LSE supported operations explicit (#171126)David Green1-468/+1590
2025-12-09Revert "[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)"pvanhout1-4/+4
2025-12-09[AArch64]SIMD fpcvt codegen for rounding nodes (#165546)Lukacma2-0/+572
2025-12-09[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)Pierre van Houtryve1-4/+4
2025-12-09[AArch64] Add intrinsics support for multi-vector FMUL (#163397)Lukacma1-0/+164
2025-12-09[AArch64][GlobalISel] Added support for neon left shift intrinsics on single-...Joshua Rodriguez3-274/+454
2025-12-09[SystemZ] Improve CCMask optimization (#171137)Dominik Steenken1-0/+28
2025-12-09[DAGCombiner] Relax nsz constraint for FP optimizations (#165011)Guy David3-4/+75
2025-12-09[SystemZ] Generate test checks (NFC)Nikita Popov2-136/+226
2025-12-09[AArch64] Run optimizeTerminators earlier too. (#170907)David Green5-124/+71
2025-12-09Revert "[Mips] Support "$sp" named register (#136821)"YunQiang Su3-832/+31
2025-12-09[X86] LowerAsmOperandForConstraint - ensure we treat L constraint immediates ...Simon Pilgrim1-0/+15
2025-12-09[AMDGPU][NPM] Enable SIModeRegister and SIInsertHardclauses passes (#168831)Vikram Hegde1-3/+3
2025-12-09[Mips] Support "$sp" named register (#136821)yingopq3-31/+832
2025-12-09[RegAlloc][AArch64] Add test case for terminal rule. NFC (#170035)hstk30-hw1-0/+136
2025-12-09[SDAG] Don't handle non-canonical libcalls in SDAG lowering (#171114)Nikita Popov7-30/+11
2025-12-09[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)Luke Lau4-1618/+2
2025-12-08[MCAsmStreamer] Print register names in --show-inst modeAlexander Richardson5-1590/+1590
2025-12-08Fix test outputting to test dir (#171255)Mircea Trofin1-1/+2
2025-12-08[AArch64] Fix missing register definitions in homogeneous epilog lowering (#1...Zhaoxuan Jiang1-0/+28
2025-12-08[NVPTX] Fix lit test issue from used_bytes_mask (#171220)Drew Kersnar3-3/+38
2025-12-09[PowerPC] Use the same lowering rule for vector rounding instructions (#166307)paperchalice1-0/+324
2025-12-08AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)Matt Arsenault3-0/+187
2025-12-08Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)Fei Peng8-539/+476
2025-12-08[LoadStoreVectorizer] Fill gaps in load/store chains to enable vectorization ...Drew Kersnar3-23/+110
2025-12-08[LLVM] Mark reloc-none test unsupported on Hexagon (#171205)Daniel Thornburgh1-0/+1
2025-12-08[X86][GlobalISel] Set Dst register correctly when narrowing G_ICMP (#169947)Evgenii Kudriashov1-6/+172
2025-12-08[AMDGPU] Fix a crash when a bool variable is used in inline asm (#171004)Shilei Tian1-0/+24
2025-12-08Fix VarArgs FixedStack object on AIX. (#170240)Sean Fertile7-62/+62
2025-12-08[DAG] Generate UMULH/SMULH with wider vector types (#170283)David Green1-237/+62
2025-12-08[AArch64] Use sve instructions for fixed-width smulh/umulh. (#166168)David Green2-120/+144
2025-12-08cmse: emit `__acle_se_` symbol for aliases to entry functions (#162109)Folkert de Vries1-0/+17
2025-12-08Fix [PowerPC] llc crashed at -O1/O2/O3: Assertion `isImm() && "Wrong MachineO...zhijian lin1-0/+22
2025-12-08[X86] Handle X86ISD::EXPAND/COMPRESS nodes as target shuffles (#171119)Simon Pilgrim2-58/+13
2025-12-08[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)Dark Steve1-3/+3
2025-12-08[X86] shift-i512.ll - extend test coverage (#171125)Simon Pilgrim1-182/+2024
2025-12-08[DAGCombiner] Don't peek through bitcast when checking isMulAddWithConstProfi...Hongyu Chen1-0/+28
2025-12-08[AMDGPU] Do not generate V_FMAC_DX9_ZERO_F32 on GFX12 (#171116)Jay Foad1-0/+82
2025-12-08[X86] vector-shuffle-combining-avx512f.ll - add tests showing failure to simp...Simon Pilgrim1-0/+69
2025-12-08[AArch64] Lower v8bf16 FMUL to BFMLAL top/bottom with +sve (#169655)Benjamin Maxwell2-20/+33
2025-12-08[AMDGPU] Add test cases for v_fmac_dx9_zero_f32 aka v_fmac_legacy_f32 (#171108)Jay Foad1-4/+36
generated by cgit v1.1 at 2026-01-08 00:28:12 +0000