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101 min.[Verifier] Make verifier fail when global variable size exceeds address space...Steffen Larsen2-2/+2
3 hours[AMDGPU] Add dot4 fp8/bf8 instructions for gfx1170 (#180516)Mirko Brkušanin1-2/+126
4 hours[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)Anshil Gandhi5-11/+1597
4 hours[AArch64] Add support for intent to read prefetch intrinsic (#179709)Kerry McLaughlin1-0/+12
4 hoursInstCombine: Use SimplifyDemandedFPClass on fmul (#177490)Matt Arsenault1-4/+2
5 hours[SDAG] Implement missing legalization for `ISD::VECTOR_FIND_LAST_ACTIVE` (#18...Benjamin Maxwell3-18/+333
6 hours[AMDGPU] Add intrinsic exposing s_alloc_vgpr (#163951)Diana Picus1-0/+123
6 hours[RISCV] Enable select optimization by default (#178394)Pengcheng Wang3-15/+32
7 hours[NewPM] Port x86-global-base-reg (#180119)Kyungtak Woo1-0/+4
8 hours[RISCV] Remove redundant czero in multi-word comparisons (#180485)Craig Topper2-74/+49
12 hoursAMDGPU/GlobalISel: Regbanklegalize rules for G_FSQRT (#179817)vangthao952-181/+414
13 hours[SPIRV] Add handling for `uinc_wrap` and `udec_wrap` atomics (#179114)Lleu Yang3-0/+78
14 hours[SPIR-V] Emit ceil(Bitwidth / 32) words during OpConstant creation (#180218)Dmitry Sidorov1-0/+30
15 hours[win][aarch64] The Windows Control Flow Guard Check function also preserves X...Daniel Paoliello1-21/+58
15 hours[RISCV] Combine shuffle of shuffles to a single shuffle (#178095)Ryan Buchner2-6/+444
16 hours[SPIRV] Implement lowering for HLSL Texture2D sampling intrinsics (#179312)Steven Perron11-0/+550
17 hours[AArch64] Inline asm v0-v31 are scalar when having less than 64-bit capacity ...Alexey Merzlyakov1-0/+166
19 hours[AMDGPU] Enable sinking of free vector ops that will be folded into their use...Gheorghe-Teodor Bercea2-12/+184
20 hours[AArch64] Add support for B and H loads/stores in LoadStoreOptimizer (#180535)John Brawn1-0/+250
21 hoursAMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_sffbh (#180099)vangthao951-19/+29
21 hoursAMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)vangthao954-0/+1772
21 hours[MIParser] - Add support for MMRAs (#180320)Ryan Mitchell2-0/+74
21 hours[RISCV] Combine ADDD+WMULSU to WMACCSU (#180454)Craig Topper1-0/+28
22 hours[X86] Fold expand(splat,passthrough,mask) -> select(splat,passthrough,mask) (...Simon Pilgrim1-12/+9
22 hours[SPIR-V] initial support for @llvm.structured.gep (#178668)Nathan Gauër7-0/+416
23 hours[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)Anshil Gandhi8-46/+479
24 hours[AMDGPU] Fix instruction size for 64-bit literal constant operands (#180387)Shilei Tian1-2/+10
24 hours[SPIRV] Fix constant materialization for width > 64bit (#180182)Dmitry Sidorov1-0/+23
24 hours[NFC][AMDGPU] Add a test to show the impact of wrong `s_mov_b64` instruction ...Shilei Tian1-0/+66
25 hours[MIPS] Fix argument size in Fast ISel (#180336)Djordje Todorovic1-0/+28
25 hours[AMDGPU] Add fp8/bf8 conversion instructions for gfx1170 (#180191)Mirko Brkušanin3-80/+374
28 hours[X86] Allow handling of i128/256/512 SELECT on the FPU (#180197)Simon Pilgrim1-491/+220
28 hours[AMDGPU] Fix V_INDIRECT_REG_READ_GPR_IDX expansion with immediate index (#179...Petr Kurapov2-0/+39
28 hoursAMDGPU: Add a test for libcall simplify pow handling (#180491)Matt Arsenault1-0/+14
29 hours[GISel] computeKnownBits - add CTLS handling (#178063)Gergo Stomfai4-13/+336
29 hours[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation (#177343)Pierre van Houtryve1-54/+74
30 hoursAMDGPU: Add syntax for s_wait_event values (#180272)Matt Arsenault1-10/+16
30 hoursAMDGPU: Add llvm.amdgcn.s.wait.event intrinsic (#180170)Matt Arsenault1-9/+42
31 hours[RISCV][CodeGen] Lower `ISD::ABS` to Zvabd instructionsPengcheng Wang5-8/+771
31 hours[RISCV][CodeGen] Lower `abds`/`abdu` to `Zvabd` instructionsPengcheng Wang3-0/+551
32 hours[RISCV][MC] Support experimental Zvabd instructionsPengcheng Wang2-0/+5
32 hours[X86] Optimized ADC + ADD to ADC (#176713)JaydeepChauhan141-5/+3
36 hours[RISCV] Add used callee-saved registers as implicit/implicit-def registers to...Jim Lin1-8/+8
36 hours[SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904)paperchalice20-1979/+4325
37 hours[llvm] Remove "no-infs-fp-math" attribute support (#180083)paperchalice1-6/+5
40 hours[RISCV] Combine ADDD with UMUL_LOHI/SMUL_LOHI into WMACCU/WMACC (#180383)Craig Topper1-0/+76
41 hours[RISCV] Add support for forming WMULSU during type legalization. (#180331)Craig Topper1-2/+27
44 hours[MIPS] musttail.ll - regenerate test checks (#180423)Simon Pilgrim1-0/+38
2 days[X86] optimize 512-bit masked truncated saturating stores (#179130)Folkert de Vries2-42/+43
3 days[AMDGPU][GlobalISel] Add lowering for G_FMODF (#180152)Alex Wang1-191/+425
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