| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-12-09 | [RISCV] Add VMNoV0 register class with only the VMaskVTs. (#171231) | Craig Topper | 8 | -23/+23 |
| 2025-12-09 | [SDAG] Don't handle non-canonical libcalls in SDAG lowering (#171114) | Nikita Popov | 2 | -6/+2 |
| 2025-12-09 | [IR][RISCV] Remove @llvm.experimental.vp.splat (#171084) | Luke Lau | 4 | -1618/+2 |
| 2025-12-08 | [DAGCombiner] Don't peek through bitcast when checking isMulAddWithConstProfi... | Hongyu Chen | 1 | -0/+28 |
| 2025-12-07 | [RISCV] Re-generate rvp-ext-rv32.ll after #170399. NFC | Craig Topper | 1 | -5/+5 |
| 2025-12-07 | [RISCV] Update P extension to the 018 version of the spec. (#170399) | Craig Topper | 5 | -1320/+25 |
| 2025-12-05 | [DAG] Fold mul 0 -> 0 when expanding mul into parts. (#168780) | David Green | 1 | -41/+25 |
| 2025-12-05 | [RISCV][llvm] Support VFADD, VFSUB, VFMUL codegen for Zvfbfa (#170612) | Brandon Wu | 8 | -479/+1965 |
| 2025-12-05 | [RISCV][llvm] Support PSLL codegen for P extension (#170074) | Brandon Wu | 2 | -0/+145 |
| 2025-12-05 | [RISCV] Inserting indirect jumps with X7 for Zicfilp (#170683) | Jesse Huang | 2 | -7/+1582 |
| 2025-12-04 | [RISCV] Use a valid AVL immediate in allone-masked-to-unmasked.mir. NFC (#170... | Craig Topper | 1 | -2/+2 |
| 2025-12-04 | [RISCV] Select (and (shl X, 8), 0xff00) -> (packh zero, X) (#170654) | Piotr Fusik | 2 | -0/+166 |
| 2025-12-04 | [DAGCombiner] Allow promoted constants in MULHU by power-of-2 -> SRL transfor... | Valeriy Savchenko | 1 | -48/+23 |
| 2025-12-04 | [RISCV] Combine vmerge_vl allones -> vmv_v_v, vmv_v_v splat(x) -> vmv_v_x (#1... | Luke Lau | 2 | -0/+90 |
| 2025-12-04 | [RISCV][GISel] Support select G_EXTRACT_SUBVECTOR (#169789) | Jianjian Guan | 1 | -0/+383 |
| 2025-12-04 | [NFC][RISCV] Cleanup unused attributes in xsfmm tests (#170601) | Brandon Wu | 15 | -88/+30 |
| 2025-12-04 | [RISCV] Commute Src in foldVMV_V_V (#170536) | Luke Lau | 2 | -0/+31 |
| 2025-12-04 | [RISCV] Emit lpad for function with returns-twice attribute (#170520) | Jesse Huang | 1 | -0/+71 |
| 2025-12-04 | [RISCV] Remove zvfh and experimental-zvfbfmin from the tests for xsfmm. (#170... | Jim Lin | 13 | -65/+52 |
| 2025-12-03 | CodeGen: Add LibcallLoweringInfo analysis pass (#168622) | Matt Arsenault | 2 | -0/+4 |
| 2025-12-03 | [RISCV] Fix corner cases after #170070 (#170438) | Pengcheng Wang | 1 | -0/+45 |
| 2025-12-03 | [RISCV][GISel] Fix legalize G_EXTRACT_SUBVECTOR (#169877) | Jianjian Guan | 1 | -28/+28 |
| 2025-12-03 | [RISCV] Sources of vmerge shouldn't overlap V0 (#170070) | Pengcheng Wang | 16 | -1006/+971 |
| 2025-12-02 | [NFC][RISCV] Correct fminimumnum test case (#170169) | Brandon Wu | 1 | -222/+222 |
| 2025-12-01 | [RISCV] Rename SFB Base Feature (#169607) | Sam Elliott | 14 | -28/+28 |
| 2025-12-01 | [RISCV] Remove the duplicate for RV32/RV64 in zicond-fp-select-zfinx.ll. NFC. | Jim Lin | 1 | -192/+97 |
| 2025-12-01 | [RISCV][llvm] Correct shamt in P extension EXTRACT_VECTOR_ELT lowering (#169823) | Brandon Wu | 2 | -0/+44 |
| 2025-12-01 | [RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (#169299) | fennecJ | 1 | -0/+798 |
| 2025-11-29 | [RISCV] Intrinsic Support for XCVelw (#129168) | Qihan Cai | 1 | -0/+27 |
| 2025-11-26 | [RISCV] Remove intrinsic declarations in tests, NFC (#167474) | Jianjian Guan | 1042 | -123974/+0 |
| 2025-11-26 | [llvm][RISCV] Support P Extension CodeGen (#167895) | Brandon Wu | 2 | -0/+97 |
| 2025-11-26 | [RISCV][llvm] Support BUILD_VECTOR codegen for P extension (#169083) | Brandon Wu | 2 | -0/+94 |
| 2025-11-25 | [RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx (#169556) | Sam Elliott | 5 | -81/+39 |
| 2025-11-25 | [RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (#169460) | Min-Yih Hsu | 1 | -0/+56 |
| 2025-11-25 | [RISCV] Add a InstRW to COPY in RISCVSchedSpacemitX60.td. (#169423) | Craig Topper | 1 | -18/+18 |
| 2025-11-24 | [RISCV] Enable rematerialization for scalar loads (#166774) | Luke Lau | 2 | -4/+169 |
| 2025-11-24 | [RISCV] Combine vslide{up,down} x, poison -> x (#169013) | Luke Lau | 2 | -0/+151 |
| 2025-11-24 | Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16... | hstk30-hw | 8 | -131/+125 |
| 2025-11-22 | [RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182) | Craig Topper | 1 | -0/+91 |
| 2025-11-23 | Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16... | Aiden Grossman | 8 | -125/+131 |
| 2025-11-23 | [RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661) | hstk30-hw | 8 | -131/+125 |
| 2025-11-22 | [DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit trunc... | Hongyu Chen | 1 | -0/+26 |
| 2025-11-21 | [RISCV] Incorporate scalar addends to extend vector multiply accumulate chain... | Ryan Buchner | 1 | -0/+143 |
| 2025-11-21 | [llvm][RISCV] Implement Zilsd load/store pair optimization (#158640) | Brandon Wu | 5 | -0/+1543 |
| 2025-11-20 | [RISCV] Do not write .s file in a test (#168865) | Mikhail Gudim | 1 | -1/+2 |
| 2025-11-20 | [RISCV][llvm] Select splat_vector(constant) with PLI (#168204) | Brandon Wu | 2 | -0/+41 |
| 2025-11-19 | [CFIInserter] Turn a reachable llvm_unreachable into a report_fatal_error. (#... | Craig Topper | 1 | -3/+4 |
| 2025-11-20 | [RISCV] Only reduce VLs of instructions with demanded VLs (#168693) | Luke Lau | 2 | -0/+37 |
| 2025-11-19 | [RISCV] Fix CFI Multiple Locations Test (#168772) | Sam Elliott | 1 | -1/+1 |
| 2025-11-19 | [RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026) | Kai Lin | 1 | -0/+54 |
