aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
AgeCommit message (Expand)AuthorFilesLines
2025-12-02Revert "[LSV] Merge contiguous chains across scalar types" (#170381)Drew Kersnar1-27/+27
2025-12-01[LSV] Merge contiguous chains across scalar types (#154069)Anshil Gandhi1-27/+27
2025-11-21Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE."...Nathan Corbyn1-2/+2
2025-11-19[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)LU-JOHN1-2/+2
2025-06-11Reland "[SelectionDAG] Make `(a & x) | (~a & y) -> (a & (x ^ y)) ^ y` availab...Iris Shi1-21/+21
2025-06-11Revert "[SelectionDAG] Make `(a & x) | (~a & y) -> (a & (x ^ y)) ^ y` availab...Iris Shi1-21/+21
2025-06-09[SelectionDAG] Make `(a & x) | (~a & y) -> (a & (x ^ y)) ^ y` available for a...Iris Shi1-21/+21
2025-05-05[AMDGPU] SIPeepholeSDWA: Handle V_CNDMASK_B32_e64 (#137930)Frederik Harwath1-2/+1
2025-03-25[AMDGPU][SelectionDAG] Use COPY instead of S_MOV_B32 to assign values to M0 (...Juan Manuel Martinez Caamaño1-9/+5
2025-03-12AMDGPU: Replace insertelement poison with insertelement undef (#130896)Matt Arsenault1-1/+1
2025-01-17DAG: Avoid forming shufflevector from a single extract_vector_elt (#122672)Matt Arsenault1-5/+5
2024-11-26AMDGPU: Remove some -verify-machineinstrs from tests (#117736)Matt Arsenault1-1/+1
2024-11-08AMDGPU: Default to selecting frame indexes to SGPRs (#115060)Matt Arsenault1-12/+12
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-1081/+1082
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-1082/+1081
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-1081/+1082
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan1-77/+76
2024-09-19[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)Pierre van Houtryve1-993/+910
2024-07-30AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)Matt Arsenault1-9/+9
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-366/+368
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-368/+366
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-366/+368
2024-02-09[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)Diana Picus1-9/+9
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song1-1/+1
2023-10-30[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)Stanislav Mekhanoshin1-20/+17
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-14/+14
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-14/+14
2023-05-26Rewrite load-store-vectorizer.Justin Lebar1-9/+9
2023-01-23AMDGPU: Clean up LDS-related occupancy calculationsNicolai Hähnle1-521/+521
2023-01-15DAG: Avoid stack lowering if bitcast has an illegal vector result typeMatt Arsenault1-6/+0
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov1-44/+44
2022-11-29[AMDGPU] Add support for new LLVM vector typesMateja Marjanovic1-16/+23
2022-10-29[DAG] Enable combineShiftOfShiftedLogic folds after type legalizationSimon Pilgrim1-174/+175
2022-10-04[AMDGPU][DAG] Fix insert_vector_elt lowering for 8 bit elementsPierre van Houtryve1-1/+1
2022-09-15[AMDGPU] Always select s_cselect_b32 for uniform 'select' SDNodeAlexander Timofeev1-44/+35
2022-09-15AMDGPU: Use GlobalPriority for largest register tuplesMatt Arsenault1-23/+23
2022-07-30[AMDGPU] Extend SILoadStoreOptimizer to s_load instructionsCarl Ritson1-52/+43
2022-06-02[AMDGPU] Improve codegen of extractelement/insertelement in some casesJulien Pages1-38/+16
2022-05-18[AMDGPU] Aggressively fold immediates in SIFoldOperandsJay Foad1-3/+2
2022-04-11[AMDGPU] Regenerate insert_vector_dynelt.llSimon Pilgrim1-270/+1912
2022-02-18[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.Jay Foad1-7/+7
2022-01-11Revert D109159 : Revert "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas1-11/+9
2022-01-05Revert "Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`.""Nico Weber1-9/+11
2022-01-05Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas1-11/+9
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow1-3/+3
2021-09-07[amdgpu] Enable selection of `s_cselect_b64`.Michael Liao1-9/+11
2021-08-25[AMDGPU] Divergence-driven compare operations instruction selectionalex-t1-29/+47
2020-09-28[AMDGPU] Make bfi patterns divergence-awareJay Foad1-11/+16
2020-06-25[AMDGPU] Select s_cselectPiotr Sobczak1-9/+13
2020-06-24Revert "[AMDGPU] Enable compare operations to be selected by divergence"Matt Arsenault1-65/+33
generated by cgit v1.1 at 2026-01-09 00:54:59 +0000