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AgeCommit message (Expand)AuthorFilesLines
2025-12-09AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)HEADmainanjenner3-585/+140
2025-12-09[AMDGPU] Scavenge a VGPR to eliminate a frame index (#166979)Anshil Gandhi1-0/+469
2025-12-09Revert "[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)"pvanhout1-4/+4
2025-12-09[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking (#162077)Pierre van Houtryve1-4/+4
2025-12-09[DAGCombiner] Relax nsz constraint for FP optimizations (#165011)Guy David2-4/+3
2025-12-09[AMDGPU][NPM] Enable SIModeRegister and SIInsertHardclauses passes (#168831)Vikram Hegde1-3/+3
2025-12-08AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)Matt Arsenault3-0/+187
2025-12-08Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" (#169614)Fei Peng8-539/+476
2025-12-08[AMDGPU] Fix a crash when a bool variable is used in inline asm (#171004)Shilei Tian1-0/+24
2025-12-08[AMDGPU][NPM] Port AMDGPUArgumentUsageInfo to NPM (#170886)Dark Steve1-3/+3
2025-12-08[AMDGPU] Do not generate V_FMAC_DX9_ZERO_F32 on GFX12 (#171116)Jay Foad1-0/+82
2025-12-08[AMDGPU] Add test cases for v_fmac_dx9_zero_f32 aka v_fmac_legacy_f32 (#171108)Jay Foad1-4/+36
2025-12-08[AMDGPU][SIInsertWaitcnts] Wait on all LDS DMA operations when no aliasing st...Pierre van Houtryve1-0/+2
2025-12-08AMDGPU/GlobalISel: Fix broken exp10 lowering for f16 (#170708)Petar Avramovic1-320/+323
2025-12-08Revert "[AMDGPU] Enable i8 GEP promotion for vector allocas" (#171087)Jan Patrick Lehr1-144/+0
2025-12-08[AMDGPU] Apply alignment attr for make.buffer.rsrc (#166914)Shoreshen1-0/+40
2025-12-08[AMDGPU] Enable i8 GEP promotion for vector allocas (#166132)Harrison Hao1-0/+144
2025-12-06Reland "AMDGPU/PromoteAlloca: Always use i32 for indexing (#170511)" (#170956)Nicolai Hähnle3-18/+24
2025-12-06[PHIElimination] Declare MachineLoopInfo dependency for Legacy PM (#169693)Dark Steve1-0/+85
2025-12-06Reland "AMDGPU/PromoteAlloca: Simplify how deferred loads work (#170510)" (#1...Nicolai Hähnle1-0/+33
2025-12-05Revert "AMDGPU/PromoteAlloca: Always use i32 for indexing (#170511)"Nicolai Hähnle3-24/+18
2025-12-05AMDGPU/PromoteAlloca: Always use i32 for indexing (#170511)Nicolai Hähnle3-18/+24
2025-12-05[AMDGPU] Make rotr illegal (#166558)Jay Foad5-211/+458
2025-12-05AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)anjenner11-46/+6165
2025-12-05AMDGPU: Improve exp10 lowering for f16 (#170771)Matt Arsenault1-166/+43
2025-12-04[AMDGPU] Update log lowering to remove contract for AMDGCN backend (#168916)Adel Ejjeh2-0/+606
2025-12-04[AMDGPU] Emit amdgpu.max_num_named_barrier resource symbol (#169851)PMylon1-0/+11
2025-12-04[LangRef] Specify icmp on pointers to only compare address (#163936)Nikita Popov1-15/+5
2025-12-04[AMDGPU][GlobalISel] Fix / workaround amdgcn.kill/.unreachable lowering (#170...Robert Imschweiler1-4/+18
2025-12-04[AMDGPU][Waitcnts] Don't create a pending flat event for LDS DMA (#170263)Sameer Sahasrabuddhe1-1/+2
2025-12-04[AMDGPU] Improve VGPR lowering test. NFC (#170633)Stanislav Mekhanoshin1-0/+65
2025-12-04AMDGPU: Fix broken exp10 lowering for f16 (#170582)Matt Arsenault1-126/+385
2025-12-04[IR] Add CallBr intrinsics support (#133907)Robert Imschweiler1-0/+101
2025-12-04[AMDGPU] Readd assertions requirement to test after #170468Aiden Grossman1-0/+1
2025-12-04expandFMINIMUMNUM_FMAXIMUMNUM: Improve compare between zeros (#140193)YunQiang Su4-22791/+18251
2025-12-03[AMDGPU] Fix VGPR lowering for V_DUAL_FMAMK_F32 (#170567)Stanislav Mekhanoshin2-2/+26
2025-12-03CodeGen: Add LibcallLoweringInfo analysis pass (#168622)Matt Arsenault1-0/+10
2025-12-03[AMDGPU] Add a RUN line to check VGPR MSBs for VOPD pairs (#170494)Jay Foad1-0/+967
2025-12-03AMDGPU: Generalize and normalize some tests to avoid future churn (#170508)Nicolai Hähnle2-10/+12
2025-12-03[Support] Support debug counters in non-assertion builds (#170468)Nikita Popov1-1/+0
2025-12-03[LowerMemIntrinsics] Factor control flow generation out of the memcpy lowerin...Fabian Ritter7-431/+403
2025-12-03[AMDGPU] Take BUF instructions into account in mayAccessScratchThroughFlat (#...Pierre van Houtryve1-21/+49
2025-12-03[NFC][AMDGPU] Refactor wave reduce test files (#170440)Aaditya8-3824/+3898
2025-12-03[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC (#170396)Stanislav Mekhanoshin1-32/+57
2025-12-02[AMDGPU] Handle phys regs in flat_scratch_base_hi operand check (#170395)Stanislav Mekhanoshin1-0/+13
2025-12-02[AMDGPU][NFC] Add occupancy checks for gfx950 and gfx1250 (#170392)Changpeng Fang1-0/+82
2025-12-02[AMDGPU] Prevent folding of flat_scr_base_hi into a 64-bit SALU (#170373)Stanislav Mekhanoshin1-0/+145
2025-12-02Revert "[LSV] Merge contiguous chains across scalar types" (#170381)Drew Kersnar40-2804/+2607
2025-12-02[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops (#168964)hjagasiaAMD1-4/+6
2025-12-02AMDGPU: Fix treating unknown mem operands as uniform (#170309)Matt Arsenault2-79/+265
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