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path: root/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
AgeCommit message (Expand)AuthorFilesLines
2025-11-25[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)Jay Foad1-191/+191
2025-11-24Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...hstk30-hw1-8/+8
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman1-8/+8
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw1-8/+8
2025-11-14AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)Matt Arsenault1-24/+24
2025-11-11AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)Matt Arsenault1-11/+10
2025-10-28[AMDGPU] Rework GFX11 VALU Mask Write Hazard (#138663)Carl Ritson1-10/+31
2025-10-22[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)LU-JOHN1-116/+94
2025-10-18Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)Jan Patrick Lehr1-94/+116
2025-10-18[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 (#162352)LU-JOHN1-116/+94
2025-10-02PeepholeOpt: Fix losing subregister indexes on full copies (#161310)Matt Arsenault1-50/+44
2025-09-04[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#1...Brox Chen1-1758/+3423
2025-08-22AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)Matt Arsenault1-1335/+675
2025-08-22AMDGPU: Expand remaining system atomic operations (#122137)Matt Arsenault1-612/+1036
2025-08-20[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154...Brox Chen1-36/+28
2025-08-18Revert "[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#1538… (#15...Brox Chen1-28/+36
2025-08-18[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#153894)Brox Chen1-36/+28
2025-07-23[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-26/+26
2025-07-09[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)Brox Chen1-46/+28
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David1-1144/+1085
2025-06-29[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)Guy David1-1085/+1144
2025-06-27[AMDGPU] Fix bad removal of s_delay_alu (#145728)Ana Mihajlovic1-2/+16
2025-04-23[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#13...Brox Chen1-1465/+2984
2025-04-22Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value ...zhijian lin1-7/+7
2025-04-21Revert "[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison valu...Nico Weber1-7/+7
2025-04-21[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in get...zhijian lin1-7/+7
2025-04-17Re apply 130577 narrow math for and operand (#133896)Shoreshen1-28/+24
2025-04-01Revert "[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable" ...Shoreshen1-24/+28
2025-04-01[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable (#130577)Shoreshen1-28/+24
2025-03-28[AMDGPU] Unused sdst writing to null (#133229)Ana Mihajlovic1-88/+88
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic1-66/+18
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata1-18/+66
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic1-66/+18
2025-02-24AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (#128388)Matt Arsenault1-0/+4241
2025-02-22PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)Matt Arsenault1-28/+28
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov1-8/+12
2025-01-30PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)Matt Arsenault1-55/+49
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson1-44/+40
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-1826/+1819
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-1819/+1826
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-1826/+1819
2024-11-05[AMDGPU] Extend type support for update_dpp intrinsic (#114597)Stanislav Mekhanoshin1-908/+848
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin1-128/+0
2024-10-07[AMDGPU] Only emit SCOPE_SYS global_wb (#110636)Pierre van Houtryve1-32/+0
2024-09-23AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)Matt Arsenault1-10/+8
2024-09-11[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)Jay Foad1-390/+368
2024-09-05[AMDGPU] V_SET_INACTIVE optimizations (#98864)Carl Ritson1-336/+200
2024-09-04[AMDGPU] Fix test update after #107108Jay Foad1-2/+2
2024-09-04[AMDGPU] Improve codegen for GFX10+ DPP reductions and scans (#107108)Jay Foad1-204/+164
2024-09-04[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)Carl Ritson1-12/+84
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