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path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2023-02-17Simplify with hasFeature. NFCFangrui Song1-5/+5
2023-02-13[ARM] Use llvm::rotl and llvm::rotr (NFC)Kazu Hirata1-1/+1
2023-01-28[Target] Use llvm::count{l,r}_{zero,one} (NFC)Kazu Hirata1-2/+2
2023-01-23[MC] Make more use of MCInstrDesc::operands. NFC.Jay Foad1-8/+8
2023-01-12[ARM] Use MCInstrInfo::get in ARMDisassembler instead of reinventing itJay Foad1-37/+40
2022-12-07[TableGen] More named sub-operands work.James Y Knight1-0/+14
2022-10-28[llvm-tblgen] NFC: Simplify DecoderEmitter.James Y Knight1-15/+0
2022-08-08[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFCFangrui Song1-4/+4
2022-08-08[llvm-objdump,ARM] Fix big-endian AArch32 disassembly.Simon Tatham1-6/+14
2022-07-26[MC,llvm-objdump,ARM] Target-dependent disassembly resync policy.Simon Tatham1-0/+30
2022-05-25[MCDisassembler] Disambiguate Size parameter in tryAddingSymbolicOperand()Maksim Panchenko1-1/+2
2022-05-15Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`Sheng1-1/+1
2022-03-25[Disassember][NFCI] Use strong type for instruction decoderMaksim Panchenko1-526/+747
2022-03-17[ARM] Fix Decode of tsb csyncArchibald Elliott1-0/+15
2021-11-30[clang][ARM] PACBTI-M assembly supportTies Stuij1-2/+65
2021-10-08Move TargetRegistry.(h|cpp) from Support to MCReid Kleckner1-1/+1
2021-09-02[ARM] Add a tail-predication loop predicate registerDavid Green1-3/+6
2021-08-16[ARM] Create MQQPR and MQQQQPR register classesDavid Green1-10/+12
2021-04-25[ARM][disassembler] Fix incorrect number of MCOperands generated by the disas...Min-Yih Hsu1-7/+8
2020-11-18ADT: Add assertions to SmallVector::insert, etc., for reference invalidationDuncan P. N. Exon Smith1-1/+2
2020-07-22[ARM] Fix Asm/Disasm of TBB/TBH instructionsDavid Spickett1-1/+3
2020-04-07[ARM] Remove condition that could never be truePeter Smith1-1/+3
2020-02-17[ARM] Add initial support for Custom Datapath Extension (CDE)Mikhail Maltsev1-1/+40
2020-01-23[ARM,MVE] Revise immediate VBIC/VORR to look more like NEON.Simon Tatham1-14/+0
2020-01-14CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2020-01-14[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio1-4/+69
2020-01-11[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song1-13/+7
2020-01-10Reverting, broke some bots. Need further investigation.Diogo Sampaio1-69/+4
2020-01-10[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio1-4/+69
2019-09-09[ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodingsOliver Stannard1-0/+6
2019-07-28[ARM] MVE VPNOTDavid Green1-0/+10
2019-07-23[ARM] Rename NEONModImm to VMOVModImm. NFCDavid Green1-4/+4
2019-07-19[ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev1-0/+7
2019-06-28[ARM] Fix integer UB in MVE load/store immediate handling.Simon Tatham1-2/+2
2019-06-27[ARM] Fix handling of zero offsets in LOB instructions.Simon Tatham1-8/+8
2019-06-27[ARM] Make coprocessor number restrictions consistent.Simon Tatham1-8/+1
2019-06-27[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.Simon Tatham1-1/+13
2019-06-25[ARM] Add remaining miscellaneous MVE instructions.Simon Tatham1-1/+22
2019-06-25[ARM] Add MVE vector load/store instructions.Simon Tatham1-0/+157
2019-06-24[ARM] Add MVE interleaving load/store family.Simon Tatham1-0/+36
2019-06-21Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.Simon Pilgrim1-1/+1
2019-06-21[ARM] Add MVE 64-bit GPR <-> vector move instructions.Simon Tatham1-0/+69
2019-06-21[ARM] Add MVE vector instructions that take a scalar input.Simon Tatham1-0/+29
2019-06-21[ARM] Add a batch of similarly encoded MVE instructions.Simon Tatham1-0/+27
2019-06-21[ARM] Fix -Wimplicit-fallthrough after D62675Fangrui Song1-0/+2
2019-06-21[ARM] Add MVE vector compare instructions.Simon Tatham1-0/+43
2019-06-21[ARM] Add a batch of MVE floating-point instructions.Simon Tatham1-0/+49
2019-06-20[ARM] Add a batch of MVE integer instructions.Simon Tatham1-0/+31
2019-06-20[llvm-objdump] Switch between ARM/Thumb based on mapping symbols.Eli Friedman1-29/+28
2019-06-19[ARM] Add MVE vector bit-operations (register inputs).Simon Tatham1-0/+14
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