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author | James Y Knight <jyknight@google.com> | 2022-11-08 17:11:04 -0500 |
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committer | James Y Knight <jyknight@google.com> | 2022-12-07 14:37:08 -0500 |
commit | 372240dfe3d5a933d9585663e15c4b6173ff23c8 (patch) | |
tree | e35f5c344bcf8f3d9ee4696df3e26c5ad6bfe19f /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
parent | b12fe0d429aa369665decd4f32175c63b542a4a1 (diff) | |
download | llvm-372240dfe3d5a933d9585663e15c4b6173ff23c8.zip llvm-372240dfe3d5a933d9585663e15c4b6173ff23c8.tar.gz llvm-372240dfe3d5a933d9585663e15c4b6173ff23c8.tar.bz2 |
[TableGen] More named sub-operands work.
Commit a538d1f13a13 first added support for named sub-operands in
CodeEmitterGen. We now add a few more features to that, enabling
further target cleanups.
1. Adds support for handling an EncoderMethod in a sub-operand in
CodeEmitterGen. Previously, the specified encoder of a sub-operand was
ignored, and only the default used.
2. Adds support for sub-operands in DecoderEmitter, along with support
for tied sub-operands.
The changes to the decoder required a few minor tweaks to a few
targets, where existing brokeness was exposed. In order to keep this
patch small, I left FIXMEs which will be addressed in upcoming
patches. (Except MIPS16, since its object file emission/decoding is
totally broken).
Differential Revision: https://reviews.llvm.org/D137653
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index cb2a0c4..b4e6b32 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -629,6 +629,9 @@ static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder); +static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder); @@ -6544,6 +6547,17 @@ static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } +[[maybe_unused]] static DecodeStatus +DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { + // Similar to above, we want to ensure that no operands are added for the + // vpred operands. (This is marked "maybe_unused" for the moment; because + // DecoderEmitter currently (wrongly) omits operands with no instruction bits, + // the decoder doesn't actually call it yet. That will be addressed in a + // future change.) + return MCDisassembler::Success; +} + static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder) { |