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authorSimon Tatham <simon.tatham@arm.com>2019-06-28 09:28:39 +0000
committerSimon Tatham <simon.tatham@arm.com>2019-06-28 09:28:39 +0000
commit29ff1b4f4653f2c77501ca4e1014c710e602aa08 (patch)
tree37ee4ac17ed5e1677c409988f8300009ab41f724 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parente662b6985a8af483a4e7c541f8b67628452d147f (diff)
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[ARM] Fix integer UB in MVE load/store immediate handling.
llvm-svn: 364635
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 9fb2fa6..673691e 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4182,7 +4182,7 @@ static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
else if (!(Val & 0x80))
imm *= -1;
if (imm != INT32_MIN)
- imm <<= shift;
+ imm *= (1U << shift);
Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
@@ -4448,7 +4448,7 @@ static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
imm *= -1;
}
if (imm != INT32_MIN)
- imm <<= shift;
+ imm *= (1U << shift);
Inst.addOperand(MCOperand::createImm(imm));
return S;