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authorMin-Yih Hsu <minyihh@uci.edu>2021-04-15 11:00:05 -0700
committerMin-Yih Hsu <minyihh@uci.edu>2021-04-25 11:55:10 -0700
commitfc86e6d188c38e2cee221fae4960c3307367f387 (patch)
tree1b1fefd35aaae835e188dea7021ad69348015e45 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parent06215023f450ce25bb608fcdb78fd1f310b23c70 (diff)
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[ARM][disassembler] Fix incorrect number of MCOperands generated by the disassembler
Try to fix bug 49974. This patch fixes two issues: 1. BL does not use predicate (BL_pred is the predicate version of BL), so we shouldn't add predicate operands in DecodeBranchImmInstruction. 2. Inside DecodeT2AddSubSPImm, we shouldn't add predicate operands into the MCInst because ARMDisassembler::AddThumbPredicate will do that for us. However, we should handle CC-out operand for t2SUBspImm and t2AddspImm. Differential Revision: https://reviews.llvm.org/D100585
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp15
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 8ea323a..51fd450 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2676,8 +2676,12 @@ DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
- if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
- return MCDisassembler::Fail;
+
+ // We already have BL_pred for BL w/ predicate, no need to add addition
+ // predicate opreands for BL
+ if (Inst.getOpcode() != ARM::BL)
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
@@ -6670,17 +6674,14 @@ static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (TypeT3) {
Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
- S = 0;
Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
} else {
Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
return MCDisassembler::Fail;
+ if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
+ return MCDisassembler::Fail;
}
- if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
- return MCDisassembler::Fail;
-
- Inst.addOperand(MCOperand::createReg(0)); // pred
return DS;
}