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13 daysReapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)sstipano2-20/+20
2026-02-09[AMDGPU][SIInsertWaitcnt][NFC] Access Waitcnt elements using InstCounterType ...vporpo2-1/+99
2026-02-09AMDGPU: Add syntax for s_wait_event values (#180272)Matt Arsenault2-0/+25
2026-02-06Revert "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321)Vladimir Vereschaka2-20/+20
2026-02-06[MC][TableGen] Expand Opcode field of MCInstrDesc (#179652)sstipano2-20/+20
2026-02-06[AMDGPU] Move magic strings used for WMMA modifiers (NFC) (#180201)Mirko BrkuĊĦanin1-0/+14
2026-02-06AMDGPU: Correct value and name for ID_RTN_SAVE_WAVE_HAS_TDM (#180181)Matt Arsenault1-1/+1
2026-01-31[AMDGPU] Introduce custom MIR formatting for s_wait_alu (#176316)vporpo2-8/+45
2026-01-26[AMDGPU] Add FeatureGFX13 and SMEM encoding for gfx13 (#177567)Mariusz Sikora3-7/+22
2026-01-20[AMDGPU] Fix inline constant encoding for `v_pk_fmac_f16` (#176659)Shilei Tian2-0/+45
2026-01-20[AMDGPU] Introduce `AMDGPUSubtargetFeature` multiclass to reduce boilerplate ...Shilei Tian1-1/+1
2026-01-17[AMDGPU][SIInsertWaitcnt] Address review feedback for waitcnt profiling expan...Pankaj Dwivedi2-4/+3
2026-01-13[LLVM] Clean up code using [not_]equal_to (NFC) (#175824)Ramkumar Ramachandra1-2/+2
2026-01-12[AMDGPU][SIInsertWaitcnt] Implement Waitcnt Expansion for Profiling (#169345)Pankaj Dwivedi2-0/+39
2026-01-09[AMDGPU] Add support for GFX12 expert scheduling mode 2 (#170319)Jay Foad2-4/+29
2025-12-17Revert "[mlir][amdgpu] Expose waitcnt bitpacking infra (#172313)" (#172636)Ivan Butygin1-1/+180
2025-12-17[mlir][amdgpu] Expose waitcnt bitpacking infra (#172313)Ivan Butygin1-180/+1
2025-12-10[AMDGPU][NFC] dump Waitcnt using an ostream operator (#171251)Sameer Sahasrabuddhe2-0/+26
2025-12-05AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)anjenner1-0/+2
2025-12-03[AMDGPU] Fix VGPR lowering for V_DUAL_FMAMK_F32 (#170567)Stanislav Mekhanoshin1-2/+11
2025-11-28[AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE (#169840)lancesix1-0/+1
2025-11-25[AMDGPU] Remove isKernelLDS, add isKernel(const Function &). NFC. (#167300)Jay Foad1-0/+2
2025-11-25[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)Jay Foad2-22/+29
2025-11-17[AMDGPU] update LDS block size for gfx1250 (#167614)Changpeng Fang1-2/+9
2025-11-14[AMDGPU] Fix wrong MSB encoding for V_FMAMK instructions (#168107)Shilei Tian1-4/+23
2025-11-11[AMDGPU] Remove implicit conversions of MCRegister to unsigned. NFC (#167284)Craig Topper2-25/+27
2025-10-16[AMDGPU][NFC] Remove a duplicate isInlinableLiteralBF16() declaration.Ivan Kosarev1-3/+0
2025-10-08[AMDGPU][MC] Avoid creating lit64() operands unless asked or needed. (#161191)Ivan Kosarev2-3/+3
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault2-18/+14
2025-10-08AMDGPU: Account for read/write register intrinsics for AGPR usage (#161988)Matt Arsenault2-6/+16
2025-10-06[AMDGPU] Remove subtarget features for dynamic VGPRs (#160822)Diana Picus1-9/+1
2025-09-25[AMDGPU] Add GFX12 wave register names with WAVE_ prefix (#144352)Aleksandar Spasojevic1-87/+79
2025-09-25AMDGPU: Ensure both wavesize features are not set (#159234)Matt Arsenault1-0/+5
2025-09-23[AMDGPU] Fix high vgpr printing with true16 (#160209)Stanislav Mekhanoshin1-1/+10
2025-09-23[AMDGPU] Add PAL metadata names for 32 user SGPRs (#160126)Jay Foad1-0/+16
2025-09-22[AMDGPU] Simplify "class HasMember##member" with llvm::is_detected (NFC) (#16...Kazu Hirata1-10/+2
2025-09-21[AMDGPU] Simplify template metaprogramming in IsMCExpr##member (NFC) (#160005)Kazu Hirata1-8/+5
2025-09-16[AMDGPU][MC] Keep MCOperands unencoded. (#158685)Ivan Kosarev2-0/+31
2025-09-15[AMDGPU][Attributor] Add `AAAMDGPUClusterDims` (#158076)Shilei Tian1-1/+1
2025-09-12[AMDGPU] Support lowering of cluster related instrinsics (#157978)Shilei Tian2-0/+92
2025-09-11[AMDGPU] Use subtarget call to determine number of VGPRs (#157927)Stanislav Mekhanoshin1-3/+6
2025-09-08[AMDGPU] Add MSG_RTN_GET_CLUSTER_BARRIER_STATE (#157549)Stanislav Mekhanoshin1-0/+2
2025-09-05[AMDGPU] Prevent VOPD combining of VGPRs with different MSBs (#157168)Stanislav Mekhanoshin1-0/+4
2025-09-04[AMDGPU] High VGPR lowering on gfx1250 (#156965)Stanislav Mekhanoshin2-0/+125
2025-09-04[AMDGPU] Ensure positive InstOffset for buffer operations (#145504)Aleksandar Spasojevic1-1/+4
2025-09-04[AMDGPU] Tail call support for whole wave functions (#145860)Diana Picus1-0/+1
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin1-1/+19
2025-09-03AMDGPU: Replace constexpr with inlineMatt Arsenault1-1/+1
2025-09-03AMDGPU: Refactor isImmOperandLegal (#155607)Matt Arsenault2-8/+8
2025-09-02[AMDGPU] Adjust VGPR allocation encoding on gfx1250 (#156546)Stanislav Mekhanoshin1-0/+3
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