aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AMDGPU/Disassembler
AgeCommit message (Expand)AuthorFilesLines
2025-11-11[AMDGPU] Remove implicit conversions of MCRegister to unsigned. NFC (#167284)Craig Topper2-7/+6
2025-10-17[AMDGPU][MC] Fix disassembler warning for v_cmpx instructions in GFX9 (#163825)Jun Wang1-0/+1
2025-10-16[AMDGPU] Preserve literal operands on disassembling. (#163376)Ivan Kosarev2-54/+83
2025-10-08[AMDGPU][MC] Avoid creating lit64() operands unless asked or needed. (#161191)Ivan Kosarev1-5/+5
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault2-5/+12
2025-10-03[AMDGPU][Disassembler] Use target feature for `.amdhsa_reserve_xnack_mask` in...Shilei Tian1-1/+4
2025-09-24[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)Ivan Kosarev2-30/+82
2025-09-11AMDGPU: Remove most manual AVLdSt decoder code (#157861)Matt Arsenault1-42/+0
2025-09-10Revert "[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)" (#157639)Pierre van Houtryve1-3/+0
2025-09-04[AMDGPU] Ensure positive InstOffset for buffer operations (#145504)Aleksandar Spasojevic2-0/+29
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin1-4/+26
2025-09-02[MC][DecoderEmitter] Fix build warning: explicit specialization cannot have a...Rahul Joshi1-6/+6
2025-09-01[AMDGPU, RISCV] Fix warningsKazu Hirata1-4/+4
2025-09-01[LLVM][MC][DecoderEmitter] Add support to specialize decoder per bitwidth (#1...Rahul Joshi2-53/+22
2025-08-22[AMDGPU] gfx1250 kernel descriptor update (#155008)Stanislav Mekhanoshin1-12/+33
2025-08-21[NFC][MC][Decoder] Extract fixed pieces of decoder code into new header file ...Rahul Joshi1-1/+2
2025-08-19[AMDGPU] upstream barrier count reporting part1 (#154409)Gang Chen1-2/+12
2025-08-05[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203)Stanislav Mekhanoshin1-0/+3
2025-08-04[AMDGPU] Add gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 MC support (#152014)Stanislav Mekhanoshin1-0/+7
2025-07-29[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)Pierre van Houtryve1-0/+3
2025-07-21AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)Changpeng Fang2-1/+47
2025-07-11[AMDGPU] MC support for v_fmaak_f64/v_fmamk_f64 gfx1250 intructions (#148282)Stanislav Mekhanoshin2-0/+28
2025-07-09[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)Stanislav Mekhanoshin2-0/+19
2025-07-09[NFC][TableGen] Change DecoderEmitter `insertBits` to use integer types only ...Rahul Joshi1-17/+1
2025-06-25[AMDGPU] Add the support for `v_cvt_f32_bf16` on gfx1250 (#145632)Shilei Tian1-5/+9
2025-06-24[AMDGPU] Support v_lshl_add_u64 in gfx1250 (#145591)Stanislav Mekhanoshin1-0/+5
2025-06-23AMDGPU: Use reportFatalUsageError for unsupported disassembly error (#145264)Matt Arsenault1-1/+1
2025-06-21[AMDGPU] Rename call instructions from b64 to i64 (#145103)Stanislav Mekhanoshin2-0/+9
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+3
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev2-56/+8
2025-05-08[AMDGPU][NFC] Get rid of OPW constants. (#139074)Ivan Kosarev2-164/+163
2025-05-08[AMDGPU][Disassembler][NFCI] Always defer immediate operands. (#138885)Ivan Kosarev2-122/+124
2025-04-18[LLVM][TableGen] Move DecoderEmitter output to anonymous namespace (#136214)Rahul Joshi2-32/+42
2025-03-19[AMDGPU] Add intrinsic and MI for image_bvh_dual_intersect_ray (#130038)Mariusz Sikora1-0/+1
2025-03-08[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (#130302)Ivan Kosarev1-15/+19
2025-02-27[AMDGPU][MC] Disassembler warning for v_cmpx instructions (#127925)Jun Wang1-1/+13
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve1-0/+1
2025-02-12[TableGen] Emit OpName as an enum class instead of a namespace (#125313)Rahul Joshi1-19/+21
2025-02-11[AMDGPU] Create new directive .amdhsa_inst_pref_size (#126622)Stanislav Mekhanoshin1-4/+4
2025-01-14[AMDGPU][True16][MC] true16 for v_cmp_lt_f16 (#122499)Brox Chen2-2/+18
2025-01-03[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (#115200)Jun Wang2-0/+26
2024-11-25AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117598)Matt Arsenault1-0/+8
2024-11-25AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#117592)Matt Arsenault1-0/+1
2024-11-25AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#117590)Matt Arsenault2-0/+2
2024-11-23AMDGPU: Remove wavefrontsize64 feature from dummy target (#117410)Matt Arsenault1-8/+8
2024-11-23AMDGPU: Move default wavesize hack for disassembler (#117422)Matt Arsenault1-18/+2
2024-11-21AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)Matt Arsenault2-0/+76
2024-11-20[AMDGPU][MC][True16] Support VOP2 instructions with true16 format (#115233)Brox Chen1-0/+19
2024-11-14[AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (#113634)Brox Chen1-8/+30
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-18/+18
generated by cgit v1.1 at 2026-01-07 17:53:16 +0000