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path: root/llvm/lib/CodeGen/MachineVerifier.cpp
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2021-08-19[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalariz...Amara Emerson1-3/+0
2021-08-18[GlobalISel] Add G_ISNANJessica Paquette1-0/+19
2021-08-13[NFC] Rename AttributeList::hasFnAttribute() -> hasFnAttr()Arthur Eubanks1-1/+1
2021-07-21[MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregsJon Roelofs1-2/+5
2021-07-20[MachineVerifier] Diagnose invalid INSERT_SUBREGsJon Roelofs1-0/+10
2021-07-16Revert "[MachineVerifier] Diagnose invalid INSERT_SUBREGs"Jon Roelofs1-9/+0
2021-07-16[MachineVerifier] Diagnose invalid INSERT_SUBREGsJon Roelofs1-0/+9
2021-06-30[GISel] Support llvm.memcpy.inlineJon Roelofs1-0/+9
2021-04-28GlobalISel: Relax verification of physical register copy typesMatt Arsenault1-15/+41
2021-04-21[CSSPGO] Exclude pseudo probe from slotindex verification.Hongtao Yu1-1/+1
2021-04-20MachineVerifier: Continue reporting errors for copiesMatt Arsenault1-2/+0
2021-04-19[Greedy RA] Add a check to MachineVerifierSerguei Katkov1-0/+9
2021-03-25[GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.Amara Emerson1-0/+11
2021-03-25[AArch64][GlobalISel] Emit bzero on DarwinJessica Paquette1-4/+6
2021-03-19[GlobalISel] Add G_SBFX + G_UBFX (bitfield extraction opcodes)Jessica Paquette1-0/+11
2021-03-08[M68k][MIR](2/8) Changes in the target-independent MIR partMin-Yih Hsu1-3/+6
2021-03-01GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sourcesMatt Arsenault1-0/+4
2021-02-17[GlobalISel] Add G_ASSERT_SEXTJessica Paquette1-8/+19
2021-02-14[llvm] Use llvm::is_contained (NFC)Kazu Hirata1-6/+2
2021-02-12[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXTJay Foad1-5/+0
2021-01-28[GlobalISel] Add G_ASSERT_ZEXTJessica Paquette1-1/+37
2021-01-21[CodeGen] Use llvm::append_range (NFC)Kazu Hirata1-2/+1
2021-01-19[llvm] Use llvm::all_of (NFC)Kazu Hirata1-10/+9
2021-01-13[Verifier] Add tied-ness verification to statepoint intsructionSerguei Katkov1-0/+16
2021-01-13[Verifier] Extend statepoint verifier to cover more constantsSerguei Katkov1-0/+7
2020-12-10[ARM][RegAlloc] Add t2LoopEndDecDavid Green1-0/+10
2020-10-20[NFC][MC] Use [MC]Register in MachineVerifierMircea Trofin1-55/+62
2020-10-15[GlobalISel] Remove scalar src from non-sequential fadd/fmul reductions.Amara Emerson1-5/+5
2020-10-14[DebugInstrRef] Parse debug instruction-references from/to MIRJeremy Morse1-0/+20
2020-10-08[GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions.Amara Emerson1-0/+34
2020-09-19Fix some clang-tidy bugprone-argument-comment issuesFangrui Song1-1/+1
2020-09-16[NFC][Regalloc] accessors for 'reg' and 'weight'Mircea Trofin1-4/+4
2020-08-27[ARM] Make MachineVerifier more strict about terminatorsSam Parker1-3/+1
2020-08-26GlobalISel: Add generic instructions for memory intrinsicsMatt Arsenault1-14/+56
2020-08-13[NewPM][CodeGen] Add machine code verification callbackYuanfang Chen1-0/+13
2020-08-11NFC. Constify MachineVerifier::verify parameterYuanfang Chen1-2/+2
2020-08-01[MachineVerifier] Refactor calcRegsPassed. NFCEvgeny Leviant1-52/+17
2020-07-29[MachineVerifier] Handle the PHI node for verifyLiveVariables()Kang Zhang1-1/+19
2020-07-16[Statepoint] Fix bug found by sanitaizer.Denis Antrushin1-3/+0
2020-07-17MIR Statepoint refactoring. Part 1: Basic MI level changes.Denis Antrushin1-0/+3
2020-07-08GlobalISel: Verify G_BITCAST changes the typeMatt Arsenault1-0/+4
2020-07-01Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.James Y Knight1-2/+1
2020-06-30GlobalISel: Disallow undef generic virtual register usesMatt Arsenault1-0/+9
2020-06-15[NFC] Add braces to if-statement in MachineVerifierDominik Montada1-1/+2
2020-06-15[MachineVerifier][GlobalISel] Check that branches have a MBB operand or are d...Dominik Montada1-0/+16
2020-06-09GlobalISel: Remove redundant check in verifierMatt Arsenault1-3/+0
2020-06-09[MachineVerifier] Add TiedOpsRewritten flag to fix verify two-address errorKang Zhang1-3/+10
2020-06-06Simplify MachineVerifier's block-successor verification.James Y Knight1-91/+47
2020-05-28[MachineVerifier] Verify that a DBG_VALUE has a debug locationVedant Kumar1-0/+7
2020-05-26GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsicMatt Arsenault1-0/+16
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