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| author | Amara Emerson <amara@apple.com> | 2020-10-09 10:41:35 -0700 |
|---|---|---|
| committer | Amara Emerson <amara@apple.com> | 2020-10-15 15:51:44 -0700 |
| commit | c2551c1f4058d2c3cc4964b1d1d0ca5946036f6c (patch) | |
| tree | 8e61f47b6ec69aefaf26454713617ebda6cff3b3 /llvm/lib/CodeGen/MachineVerifier.cpp | |
| parent | edbdea7466d25c5e4d9f73e3043ac87efe433193 (diff) | |
| download | llvm-c2551c1f4058d2c3cc4964b1d1d0ca5946036f6c.zip llvm-c2551c1f4058d2c3cc4964b1d1d0ca5946036f6c.tar.gz llvm-c2551c1f4058d2c3cc4964b1d1d0ca5946036f6c.tar.bz2 | |
[GlobalISel] Remove scalar src from non-sequential fadd/fmul reductions.
It's probably better to split these into separate G_FADD/G_FMUL + G_VECREDUCE
operations in the translator rather than carrying the scalar around. The
majority of the time it'll get simplified away as the scalars are probably
identity values.
Differential Revision: https://reviews.llvm.org/D89150
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 5c22673..cf48d29 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1489,20 +1489,20 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { break; } case TargetOpcode::G_VECREDUCE_SEQ_FADD: - case TargetOpcode::G_VECREDUCE_SEQ_FMUL: - case TargetOpcode::G_VECREDUCE_FADD: - case TargetOpcode::G_VECREDUCE_FMUL: { + case TargetOpcode::G_VECREDUCE_SEQ_FMUL: { LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg()); LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg()); if (!DstTy.isScalar()) report("Vector reduction requires a scalar destination type", MI); if (!Src1Ty.isScalar()) - report("FADD/FMUL vector reduction requires a scalar 1st operand", MI); + report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI); if (!Src2Ty.isVector()) - report("FADD/FMUL vector reduction must have a vector 2nd operand", MI); + report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI); break; } + case TargetOpcode::G_VECREDUCE_FADD: + case TargetOpcode::G_VECREDUCE_FMUL: case TargetOpcode::G_VECREDUCE_FMAX: case TargetOpcode::G_VECREDUCE_FMIN: case TargetOpcode::G_VECREDUCE_ADD: |