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| author | Jon Roelofs <jonathan_roelofs@apple.com> | 2021-06-29 17:56:18 -0700 |
|---|---|---|
| committer | Jon Roelofs <jonathan_roelofs@apple.com> | 2021-06-30 12:39:05 -0700 |
| commit | a64287247633da36b58d65e4c5e248f2b4c6fe61 (patch) | |
| tree | c7dab054c453be603910b48cd7780e8f0f714b9c /llvm/lib/CodeGen/MachineVerifier.cpp | |
| parent | 2eb7bbbe65b6374e6137772f1c2c46e6daa5c33d (diff) | |
| download | llvm-a64287247633da36b58d65e4c5e248f2b4c6fe61.zip llvm-a64287247633da36b58d65e4c5e248f2b4c6fe61.tar.gz llvm-a64287247633da36b58d65e4c5e248f2b4c6fe61.tar.bz2 | |
[GISel] Support llvm.memcpy.inline
Differential revision: https://reviews.llvm.org/D105072
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index cb098ac..6b8c9f4 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1477,6 +1477,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { } break; } + case TargetOpcode::G_MEMCPY_INLINE: case TargetOpcode::G_MEMCPY: case TargetOpcode::G_MEMMOVE: { ArrayRef<MachineMemOperand *> MMOs = MI->memoperands(); @@ -1507,6 +1508,10 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace()) report("inconsistent load address space", MI); + if (Opc != TargetOpcode::G_MEMCPY_INLINE) + if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL)) + report("'tail' flag (operand 3) must be an immediate 0 or 1", MI); + break; } case TargetOpcode::G_BZERO: @@ -1532,6 +1537,10 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace()) report("inconsistent " + Twine(Name, " address space"), MI); + if (!MI->getOperand(MI->getNumOperands() - 1).isImm() || + (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL)) + report("'tail' flag (last operand) must be an immediate 0 or 1", MI); + break; } case TargetOpcode::G_VECREDUCE_SEQ_FADD: |