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| author | Amara Emerson <amara@apple.com> | 2021-03-24 23:59:40 -0700 |
|---|---|---|
| committer | Amara Emerson <amara@apple.com> | 2021-03-25 17:23:30 -0700 |
| commit | 55533203d72e6f08b083f369ab5e31e139f2ef48 (patch) | |
| tree | e5b5624cfac9faa3a859f497725d108612ef69f2 /llvm/lib/CodeGen/MachineVerifier.cpp | |
| parent | 23f657c165da1b599d79de11980583968d8e6a91 (diff) | |
| download | llvm-55533203d72e6f08b083f369ab5e31e139f2ef48.zip llvm-55533203d72e6f08b083f369ab5e31e139f2ef48.tar.gz llvm-55533203d72e6f08b083f369ab5e31e139f2ef48.tar.bz2 | |
[GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.
Differential Revision: https://reviews.llvm.org/D99383
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 9966600..503cd52 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1578,6 +1578,17 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { } break; } + case TargetOpcode::G_ROTR: + case TargetOpcode::G_ROTL: { + LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg()); + LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg()); + if (Src1Ty.isVector() != Src2Ty.isVector()) { + report("Rotate requires operands to be either all scalars or all vectors", + MI); + break; + } + break; + } default: break; |