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authorKang Zhang <shkzhang@cn.ibm.com>2020-07-29 15:43:47 +0000
committerKang Zhang <shkzhang@cn.ibm.com>2020-07-29 15:43:47 +0000
commita4ade9ed21e55946c52961a549ca4d23f9058b08 (patch)
tree7d165d5d0aecc2ab84b4e8b168ec93709fcb849e /llvm/lib/CodeGen/MachineVerifier.cpp
parentd42c7b22118c763090e3bec180cb8f01b5c4cfeb (diff)
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[MachineVerifier] Handle the PHI node for verifyLiveVariables()
Summary: When doing MachineVerifier for LiveVariables, the MachineVerifier pass will calculate the LiveVariables, and compares the result with the result livevars pass gave. If they are different, verifyLiveVariables() will give error. But when we calculate the LiveVariables in MachineVerifier, we don't consider the PHI node, while livevars considers. This patch is to fix above bug. Reviewed By: bjope Differential Revision: https://reviews.llvm.org/D80274
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp20
1 files changed, 19 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index c1a2c4e..e45e696 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -132,7 +132,8 @@ namespace {
bool reachable = false;
// Vregs that must be live in because they are used without being
- // defined. Map value is the user.
+ // defined. Map value is the user. vregsLiveIn doesn't include regs
+ // that only are used by PHI nodes.
RegMap vregsLiveIn;
// Regs killed in MBB. They may be defined again, and will then be in both
@@ -2302,6 +2303,23 @@ void MachineVerifier::calcRegsRequired() {
if (PInfo.addRequired(MInfo.vregsLiveIn))
todo.insert(Pred);
}
+
+ // Handle the PHI node.
+ for (const MachineInstr &MI : MBB.phis()) {
+ for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
+ // Skip those Operands which are undef regs or not regs.
+ if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
+ continue;
+
+ // Get register and predecessor for one PHI edge.
+ Register Reg = MI.getOperand(i).getReg();
+ const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
+
+ BBInfo &PInfo = MBBInfoMap[Pred];
+ if (PInfo.addRequired(Reg))
+ todo.insert(Pred);
+ }
+ }
}
// Iteratively push vregsRequired to predecessors. This will converge to the