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AgeCommit message (Expand)AuthorFilesLines
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich2-3/+3
2023-11-16aarch64: Add support for VMSA feature enhancements.Srinath Parvathaneni1-0/+25
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni1-0/+9
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-0/+14
2023-11-16aarch64: Add features to the Statistical Profiling Extension.Srinath Parvathaneni1-0/+1
2023-11-16aarch64: Add SLC target for PRFM instruction.Srinath Parvathaneni1-6/+6
2023-11-15Finalized intl-update patchesArsen Arsenovi?7-334/+2410
2023-11-10Add support for ilp32 register alias.Lulu Cai2-6/+6
2023-11-09aarch64: Fix error in THE system register checkingVictor Do Nascimento2-4/+1
2023-11-09x86: rework UWRMSR operand swappingJan Beulich2-3/+5
2023-11-09x86: do away with is_evex_encoding()Jan Beulich2-575/+585
2023-11-09x86: split insn templates' CPU fieldJan Beulich4-474/+4249
2023-11-09x86: Cpu64 handling improvementsJan Beulich3-52/+90
2023-11-09x86: Intel Core processors do not support CMPXCHG16BJan Beulich2-2/+2
2023-11-07aarch64: Add LSE128 instructionsVictor Do Nascimento4-2407/+2558
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+5
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento3-0/+8
2023-11-07aarch64: Add 128-bit system register flagsVictor Do Nascimento2-10/+13
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento3-0/+10
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett2-0/+39
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett2-0/+37
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-19/+19
2023-11-02aarch64: Add GCS system registers.Srinath Parvathaneni1-0/+10
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni5-2235/+2248
2023-11-02aarch64: Add support for GCS extension.srinath4-2510/+2559
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni2-0/+11
2023-10-31Support Intel USER_MSRHu, Lin17-1166/+1314
2023-10-30aarch64: Update aarch64-sys-regs.def headerVictor Do Nascimento1-0/+4
2023-10-28opcodes: bpf-dis.c: fix typo in commentJose E. Marchesi1-1/+1
2023-10-19opcodes: microblaze: Fix bit masking bugNeal Frager2-6/+9
2023-10-15opcodes: microblaze: Add new bit-field instructionsNeal Frager3-3/+39
2023-10-13RISC-V: Add support for numbered ISA mapping stringsJoseph Faulls1-1/+15
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager3-32/+2
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager3-2/+32
2023-10-05microblaze: Add address extension instructionsNeal frager3-10/+23
2023-10-04opcodes: microblaze: Add hibernate and suspend instructionsNeal frager3-1/+13
2023-10-04aarch64: Refactor system register dataVictor Do Nascimento2-1068/+1080
2023-10-04aarch64: system register aliasing detectionVictor Do Nascimento2-1/+11
2023-09-27opcodes: microblaze: Add wdc.ext.clear and wdc.ext.flush insnsNeal Frager2-17/+20
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich2-1183/+512
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich2-327/+207
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich2-1028/+662
2023-09-27Add support for "pcaddi rd, symbol"mengqinggang1-1/+1
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford3-94/+85
2023-09-25Revert "arc: Add new opcode functions for ARCv3 ISA."Claudiu Zissulescu15-3872/+3091
2023-09-25Revert "arc: New ARCv3 ISA instruction table"Claudiu Zissulescu1-11422/+0
2023-09-25arc: New ARCv3 ISA instruction tableClaudiu Zissulescu1-0/+11422
2023-09-25arc: Add new opcode functions for ARCv3 ISA.Claudiu Zissulescu15-3091/+3872
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich4-2671/+2670
2023-09-14x86: Vxy naming correctionJan Beulich1-5/+5
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