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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-10-30 12:39:28 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-07 21:54:19 +0000 |
| commit | f0d70d8ee63b6f6a59cf4a10268f546b0bc80777 (patch) | |
| tree | 7b830773e473658e78fcf3acebba7ebfcf961e4b /opcodes | |
| parent | 6219f9dae7d04b52ef171e0aa3341bf977b05a68 (diff) | |
| download | gdb-f0d70d8ee63b6f6a59cf4a10268f546b0bc80777.zip gdb-f0d70d8ee63b6f6a59cf4a10268f546b0bc80777.tar.gz gdb-f0d70d8ee63b6f6a59cf4a10268f546b0bc80777.tar.bz2 | |
aarch64: Add arch support for LSE128 extension
Enable the `+lse128' feature modifier which, together with new
internal feature flags, enables LSE128 instructions, which are
represented via the new `_LSE128_INSN' macro.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_features): Add new "lse128"
entry.
include/ChangeLog:
* include/opcode/aarch64.h (enum aarch64_feature_bit): New
AARCH64_FEATURE_LSE128 feature bit.
(enum aarch64_insn_class): New lse128_atomic instruction class.
opcodes/ChangeLog:
* opcodes/aarch64-tbl.h (aarch64_feature_lse128): New.
(LSE128): Likewise.
(_LSE128_INSN): Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index bc38542..752972a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2470,6 +2470,8 @@ static const aarch64_feature_set aarch64_feature_crc = AARCH64_FEATURE (CRC); static const aarch64_feature_set aarch64_feature_lse = AARCH64_FEATURE (LSE); +static const aarch64_feature_set aarch64_feature_lse128 = + AARCH64_FEATURES (2, LSE, LSE128); static const aarch64_feature_set aarch64_feature_lor = AARCH64_FEATURE (LOR); static const aarch64_feature_set aarch64_feature_rdma = @@ -2584,6 +2586,7 @@ static const aarch64_feature_set aarch64_feature_the = #define SIMD &aarch64_feature_simd #define CRC &aarch64_feature_crc #define LSE &aarch64_feature_lse +#define LSE128 &aarch64_feature_lse128 #define LOR &aarch64_feature_lor #define RDMA &aarch64_feature_rdma #define FP_F16 &aarch64_feature_fp_f16 @@ -2652,6 +2655,8 @@ static const aarch64_feature_set aarch64_feature_the = { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL } +#define _LSE128_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, LSE128, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL } #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |