RISC-V: Add support for XCVmac extension in CV32E40P

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
	* testsuite/gas/riscv/cv-mac-insns.d: New test.
	* testsuite/gas/riscv/cv-mac-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble information with
          the EXTRACT macro implemented.
	* riscv-opc.c: Defined the MASK and added
          XCVmac instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCVmac.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for uimm.
	(enum riscv_insn_class): Added the XCVmac instruction class.

2 files changed, 37 insertions, 0 deletions

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 216916e..275e715 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -677,6 +677,17 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		  }
 	      }
 	      break;
+	    case 'c': /* Vendor-specific (CORE-V) operands.  */
+	      switch (*++oparg)
+		{
+		  case '3':
+		    print (info->stream, dis_style_immediate, "%d",
+			((int) EXTRACT_CV_IS3_UIMM5 (l)));
+		    break;
+		  default:
+		    goto undefined_modifier;
+		}
+	      break;
 	    default:
 	      goto undefined_modifier;
 	    }
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8d92d8b..8aee51c 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -154,6 +154,8 @@ const float riscv_fli_numval[32] =
 #define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
 #define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
 #define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
+/* Vendor-specific (CORE-V) masks.  */
+#define MASK_CV_IS3_UIMM5 ENCODE_CV_IS3_UIMM5 (-1U)
 
 static int
 match_opcode (const struct riscv_opcode *op, insn_t insn)
@@ -2039,6 +2041,30 @@ const struct riscv_opcode riscv_opcodes[] =
 {"hsv.w",       0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
 {"hsv.d",      64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
 
+/* Vendor-specific (CORE-V) Xcvmac instructions.  */
+{"cv.mac",      0, INSN_CLASS_XCVMAC, "d,s,t",     MATCH_CV_MAC,      MASK_CV_MAC, match_opcode, 0},
+{"cv.msu",      0, INSN_CLASS_XCVMAC, "d,s,t",     MATCH_CV_MSU,      MASK_CV_MSU, match_opcode, 0},
+{"cv.mulsn",    0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSN,    MASK_CV_MULSN, match_opcode, 0},
+{"cv.muls",     0, INSN_CLASS_XCVMAC, "d,s,t",     MATCH_CV_MULSN,    MASK_CV_MULSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulsrn",   0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULSRN,   MASK_CV_MULSRN, match_opcode, 0},
+{"cv.mulhhsn",  0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSN,  MASK_CV_MULHHSN, match_opcode, 0},
+{"cv.mulhhs",   0, INSN_CLASS_XCVMAC, "d,s,t",     MATCH_CV_MULHHSN,  MASK_CV_MULHHSN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHSRN, MASK_CV_MULHHSRN, match_opcode, 0},
+{"cv.mulun",    0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULUN,    MASK_CV_MULUN, match_opcode, 0},
+{"cv.mulu",     0, INSN_CLASS_XCVMAC, "d,s,t",     MATCH_CV_MULUN,    MASK_CV_MULUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulurn",   0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULURN,   MASK_CV_MULURN, match_opcode, 0},
+{"cv.mulhhun",  0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHUN,  MASK_CV_MULHHUN, match_opcode, 0},
+{"cv.mulhhu",   0, INSN_CLASS_XCVMAC, "d,s,t",     MATCH_CV_MULHHUN,  MASK_CV_MULHHUN|MASK_CV_IS3_UIMM5, match_opcode, INSN_ALIAS},
+{"cv.mulhhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MULHHURN, MASK_CV_MULHHURN, match_opcode, 0},
+{"cv.macsn",    0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSN,    MASK_CV_MACSN, match_opcode, 0},
+{"cv.machhsn",  0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSN,  MASK_CV_MACHHSN, match_opcode, 0},
+{"cv.macsrn",   0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACSRN,   MASK_CV_MACSRN, match_opcode, 0},
+{"cv.machhsrn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHSRN, MASK_CV_MACHHSRN, match_opcode, 0},
+{"cv.macun",    0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACUN,    MASK_CV_MACUN, match_opcode, 0},
+{"cv.machhun",  0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHUN,  MASK_CV_MACHHUN, match_opcode, 0},
+{"cv.macurn",   0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACURN,   MASK_CV_MACURN, match_opcode, 0},
+{"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,Xc3", MATCH_CV_MACHHURN, MASK_CV_MACHHURN, match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},