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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2023-11-16 14:27:25 +0000 |
|---|---|---|
| committer | srinath <srinath.parvathaneni@arm.com> | 2023-11-16 14:29:30 +0000 |
| commit | 44167ca8da9aada2e574525e0548347f80442b09 (patch) | |
| tree | 91be08040fca57f4052e70a0649e38b718947549 /opcodes | |
| parent | 281fda33bcf47d5d541e28aac1e5772ebdf1eb1a (diff) | |
| download | gdb-44167ca8da9aada2e574525e0548347f80442b09.zip gdb-44167ca8da9aada2e574525e0548347f80442b09.tar.gz gdb-44167ca8da9aada2e574525e0548347f80442b09.tar.bz2 | |
aarch64: Add support for VMSA feature enhancements.
This patch adds the permission model enhancement and memory
attribute index enhancement features and their corresponding
system registers in AArch64 assembler.
Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
Memory Attribute Index Enhancement (FEAT_AIE)
Extension to Translation Control Registers (FEAT_TCR2)
These features are available by default from Armv9.4-A architecture.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-sys-regs.def | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index b51c5aa..0f647ef 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -54,6 +54,10 @@ SYSREG ("amair_el12", CPENC (3,5,10,3,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A)) SYSREG ("amair_el2", CPENC (3,4,10,3,0), 0, AARCH64_NO_FEATURES) SYSREG ("amair_el3", CPENC (3,6,10,3,0), 0, AARCH64_NO_FEATURES) + SYSREG ("amair2_el1", CPENC (3,0,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) + SYSREG ("amair2_el12", CPENC (3,5,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) + SYSREG ("amair2_el2", CPENC (3,4,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) + SYSREG ("amair2_el3", CPENC (3,6,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) SYSREG ("amcfgr_el0", CPENC (3,3,13,2,1), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A)) SYSREG ("amcg1idr_el0", CPENC (3,3,13,2,6), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_6A)) SYSREG ("amcgcr_el0", CPENC (3,3,13,2,2), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A)) @@ -556,6 +560,10 @@ SYSREG ("mair_el12", CPENC (3,5,10,2,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A)) SYSREG ("mair_el2", CPENC (3,4,10,2,0), 0, AARCH64_NO_FEATURES) SYSREG ("mair_el3", CPENC (3,6,10,2,0), 0, AARCH64_NO_FEATURES) + SYSREG ("mair2_el1", CPENC (3,0,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) + SYSREG ("mair2_el12", CPENC (3,5,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) + SYSREG ("mair2_el2", CPENC (3,4,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) + SYSREG ("mair2_el3", CPENC (3,6,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE)) SYSREG ("mdccint_el1", CPENC (2,0,0,2,0), 0, AARCH64_NO_FEATURES) SYSREG ("mdccsr_el0", CPENC (2,3,0,1,0), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("mdcr_el2", CPENC (3,4,1,1,1), 0, AARCH64_NO_FEATURES) @@ -600,6 +608,13 @@ SYSREG ("oseccr_el1", CPENC (2,0,0,6,2), 0, AARCH64_NO_FEATURES) SYSREG ("oslar_el1", CPENC (2,0,1,0,4), F_REG_WRITE, AARCH64_NO_FEATURES) SYSREG ("oslsr_el1", CPENC (2,0,1,1,4), F_REG_READ, AARCH64_NO_FEATURES) + SYSREG ("pir_el1", CPENC (3,0,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE)) + SYSREG ("pir_el12", CPENC (3,5,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE)) + SYSREG ("pir_el2", CPENC (3,4,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE)) + SYSREG ("pir_el3", CPENC (3,6,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE)) + SYSREG ("pire0_el1", CPENC (3,0,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE)) + SYSREG ("pire0_el12", CPENC (3,5,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE)) + SYSREG ("pire0_el2", CPENC (3,4,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE)) SYSREG ("pan", CPENC (3,0,4,2,3), F_ARCHEXT, AARCH64_FEATURE (PAN)) SYSREG ("par_el1", CPENC (3,0,7,4,0), F_REG_128, AARCH64_NO_FEATURES) SYSREG ("pfar_el1", CPENC (3,0,6,0,5), F_ARCHEXT, AARCH64_FEATURE (PFAR)) @@ -699,6 +714,11 @@ SYSREG ("pmuserenr_el0", CPENC (3,3,9,14,0), 0, AARCH64_NO_FEATURES) SYSREG ("pmxevcntr_el0", CPENC (3,3,9,13,2), 0, AARCH64_NO_FEATURES) SYSREG ("pmxevtyper_el0", CPENC (3,3,9,13,1), 0, AARCH64_NO_FEATURES) + SYSREG ("por_el0", CPENC (3,3,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE)) + SYSREG ("por_el1", CPENC (3,0,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE)) + SYSREG ("por_el12", CPENC (3,5,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE)) + SYSREG ("por_el2", CPENC (3,4,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE)) + SYSREG ("por_el3", CPENC (3,6,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE)) SYSREG ("prbar10_el1", CPENC (3,0,6,13,0), F_ARCHEXT, AARCH64_FEATURE (V8R)) SYSREG ("prbar10_el2", CPENC (3,4,6,13,0), F_ARCHEXT, AARCH64_FEATURE (V8R)) SYSREG ("prbar11_el1", CPENC (3,0,6,13,4), F_ARCHEXT, AARCH64_FEATURE (V8R)) @@ -818,11 +838,16 @@ SYSREG ("spsr_und", CPENC (3,4,4,3,2), 0, AARCH64_NO_FEATURES) SYSREG ("ssbs", CPENC (3,3,4,2,6), F_ARCHEXT, AARCH64_FEATURE (SSBS)) SYSREG ("svcr", CPENC (3,3,4,2,2), F_ARCHEXT, AARCH64_FEATURE (SME)) + SYSREG ("s2pir_el2", CPENC (3,4,10,2,5), F_ARCHEXT, AARCH64_FEATURE (S2PIE)) + SYSREG ("s2por_el1", CPENC (3,0,10,2,5), F_ARCHEXT, AARCH64_FEATURE (S2POE)) SYSREG ("tco", CPENC (3,3,4,2,7), F_ARCHEXT, AARCH64_FEATURE (MEMTAG)) SYSREG ("tcr_el1", CPENC (3,0,2,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tcr_el12", CPENC (3,5,2,0,2), F_ARCHEXT, AARCH64_FEATURE (V8_1A)) SYSREG ("tcr_el2", CPENC (3,4,2,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tcr_el3", CPENC (3,6,2,0,2), 0, AARCH64_NO_FEATURES) + SYSREG ("tcr2_el1", CPENC (3,0,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2)) + SYSREG ("tcr2_el12", CPENC (3,5,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2)) + SYSREG ("tcr2_el2", CPENC (3,4,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2)) SYSREG ("teecr32_el1", CPENC (2,2,0,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("teehbr32_el1", CPENC (2,2,1,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("tfsr_el1", CPENC (3,0,5,6,0), F_ARCHEXT, AARCH64_FEATURE (MEMTAG)) |