aboutsummaryrefslogtreecommitdiff
path: root/opcodes/aarch64-asm-2.c
AgeCommit message (Expand)AuthorFilesLines
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-38/+39
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-11/+12
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-10/+11
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-33/+34
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-19/+20
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-137/+138
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-76/+77
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das1-295/+295
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das1-316/+316
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-348/+346
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-346/+348
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-316/+316
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-386/+388
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin...Sudakshina Das1-356/+360
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-533/+535
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-151/+153
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-135/+139
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-93/+93
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das1-450/+450
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton1-94/+99
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-68/+69
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-1/+1
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-59/+60
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-56/+57
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-105/+106
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-88/+94
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-72/+81
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-2/+2
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-506/+510
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-318/+318
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-306/+306
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-324/+326
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-406/+406
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-399/+400
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-389/+389
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-127/+140
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+119
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-10/+16
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-25/+32
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-38/+62
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-18/+27
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-19/+57
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-6/+8
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-5/+7
generated by cgit v1.1 at 2024-11-28 10:21:10 +0000