[AArch64][SVE 26/32] Add SVE MUL VL addressing modes

This patch adds support for addresses of the form:

       [<base>, #<offset>, MUL VL]

This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.

For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, ....  The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
	(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
	(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
	operands.
	* aarch64-opc.c (aarch64_operand_modifiers): Initialize
	the AARCH64_MOD_MUL_VL entry.
	(value_aligned_p): Cope with non-power-of-two alignments.
	(operand_general_constraint_met_p): Handle the new MUL VL addresses.
	(print_immediate_offset_address): Likewise.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
	(ins_sve_addr_ri_s9xvl): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
	(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
	(ext_sve_addr_ri_s9xvl): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
	(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
	parse_shift_modes.
	(parse_shift): Handle SHIFTED_MUL_VL.
	(parse_address_main): Add an imm_shift_mode parameter.
	(parse_address, parse_sve_address): Update accordingly.
	(parse_operands): Handle MUL VL addressing modes.

1 files changed, 27 insertions, 18 deletions

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 47a414c..da590ca 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -480,12 +480,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 27:
     case 35:
     case 36:
-    case 123:
-    case 124:
-    case 125:
-    case 126:
-    case 127:
-    case 128:
     case 129:
     case 130:
     case 131:
@@ -494,7 +488,13 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 134:
     case 135:
     case 136:
+    case 137:
+    case 138:
     case 139:
+    case 140:
+    case 141:
+    case 142:
+    case 145:
       return aarch64_ins_regno (self, info, code, inst);
     case 12:
       return aarch64_ins_reg_extended (self, info, code, inst);
@@ -531,8 +531,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 68:
     case 69:
     case 70:
-    case 120:
-    case 122:
+    case 126:
+    case 128:
       return aarch64_ins_imm (self, info, code, inst);
     case 38:
     case 39:
@@ -587,46 +587,55 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 90:
     case 91:
     case 92:
-      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
+      return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
     case 93:
+      return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
     case 94:
+      return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
     case 95:
     case 96:
     case 97:
     case 98:
+      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
     case 99:
     case 100:
     case 101:
     case 102:
     case 103:
     case 104:
-      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
     case 105:
     case 106:
     case 107:
     case 108:
     case 109:
     case 110:
+      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
     case 111:
     case 112:
-      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
     case 113:
     case 114:
     case 115:
     case 116:
-      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
     case 117:
-      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
     case 118:
-      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
+      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
     case 119:
-      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
+    case 120:
     case 121:
+    case 122:
+      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
+    case 123:
+      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
+    case 124:
+      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
+    case 125:
+      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
+    case 127:
       return aarch64_ins_sve_scale (self, info, code, inst);
-    case 137:
+    case 143:
       return aarch64_ins_sve_index (self, info, code, inst);
-    case 138:
-    case 140:
+    case 144:
+    case 146:
       return aarch64_ins_sve_reglist (self, info, code, inst);
     default: assert (0); abort ();
     }