[AArch64][SVE 31/32] Add SVE instructions

This patch adds the SVE instruction definitions and associated OP_*
enum values.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
	(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
	(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
	(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.

opcodes/
	* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
	(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
	(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
	(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
	(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
	(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
	(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
	(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
	(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
	(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
	(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
	(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
	(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
	(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
	(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
	(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
	(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
	(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
	(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
	(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
	(OP_SVE_XWU, OP_SVE_XXU): New macros.
	(aarch64_feature_sve): New variable.
	(SVE): New macro.
	(_SVE_INSN): Likewise.
	(aarch64_opcode_table): Add SVE instructions.
	* aarch64-opc.h (extract_fields): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.c (extract_fields): Make global.
	(do_misc_decoding): Handle the new SVE aarch64_ops.
	* aarch64-dis-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document the "sve" feature.
	* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
	(get_reg_expected_msg): Handle it.
	(parse_operands): When parsing operands of an SVE instruction,
	disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
	(aarch64_features): Add an entry for SVE.

1 files changed, 119 insertions, 0 deletions

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 5dd6a81..5977a66 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -440,6 +440,125 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 1131:	/* sys */
       value = 1131;	/* --> sys.  */
       break;
+    case 1881:	/* bic */
+    case 1186:	/* and */
+      value = 1186;	/* --> and.  */
+      break;
+    case 1169:	/* mov */
+    case 1188:	/* and */
+      value = 1188;	/* --> and.  */
+      break;
+    case 1173:	/* movs */
+    case 1189:	/* ands */
+      value = 1189;	/* --> ands.  */
+      break;
+    case 1882:	/* cmple */
+    case 1224:	/* cmpge */
+      value = 1224;	/* --> cmpge.  */
+      break;
+    case 1885:	/* cmplt */
+    case 1227:	/* cmpgt */
+      value = 1227;	/* --> cmpgt.  */
+      break;
+    case 1883:	/* cmplo */
+    case 1229:	/* cmphi */
+      value = 1229;	/* --> cmphi.  */
+      break;
+    case 1884:	/* cmpls */
+    case 1232:	/* cmphs */
+      value = 1232;	/* --> cmphs.  */
+      break;
+    case 1166:	/* mov */
+    case 1254:	/* cpy */
+      value = 1254;	/* --> cpy.  */
+      break;
+    case 1168:	/* mov */
+    case 1255:	/* cpy */
+      value = 1255;	/* --> cpy.  */
+      break;
+    case 1892:	/* fmov */
+    case 1171:	/* mov */
+    case 1256:	/* cpy */
+      value = 1256;	/* --> cpy.  */
+      break;
+    case 1161:	/* mov */
+    case 1268:	/* dup */
+      value = 1268;	/* --> dup.  */
+      break;
+    case 1163:	/* mov */
+    case 1160:	/* mov */
+    case 1269:	/* dup */
+      value = 1269;	/* --> dup.  */
+      break;
+    case 1891:	/* fmov */
+    case 1165:	/* mov */
+    case 1270:	/* dup */
+      value = 1270;	/* --> dup.  */
+      break;
+    case 1164:	/* mov */
+    case 1271:	/* dupm */
+      value = 1271;	/* --> dupm.  */
+      break;
+    case 1886:	/* eon */
+    case 1273:	/* eor */
+      value = 1273;	/* --> eor.  */
+      break;
+    case 1174:	/* not */
+    case 1275:	/* eor */
+      value = 1275;	/* --> eor.  */
+      break;
+    case 1175:	/* nots */
+    case 1276:	/* eors */
+      value = 1276;	/* --> eors.  */
+      break;
+    case 1887:	/* facle */
+    case 1281:	/* facge */
+      value = 1281;	/* --> facge.  */
+      break;
+    case 1888:	/* faclt */
+    case 1282:	/* facgt */
+      value = 1282;	/* --> facgt.  */
+      break;
+    case 1889:	/* fcmle */
+    case 1291:	/* fcmge */
+      value = 1291;	/* --> fcmge.  */
+      break;
+    case 1890:	/* fcmlt */
+    case 1293:	/* fcmgt */
+      value = 1293;	/* --> fcmgt.  */
+      break;
+    case 1158:	/* fmov */
+    case 1299:	/* fcpy */
+      value = 1299;	/* --> fcpy.  */
+      break;
+    case 1157:	/* fmov */
+    case 1316:	/* fdup */
+      value = 1316;	/* --> fdup.  */
+      break;
+    case 1159:	/* mov */
+    case 1614:	/* orr */
+      value = 1614;	/* --> orr.  */
+      break;
+    case 1893:	/* orn */
+    case 1615:	/* orr */
+      value = 1615;	/* --> orr.  */
+      break;
+    case 1162:	/* mov */
+    case 1617:	/* orr */
+      value = 1617;	/* --> orr.  */
+      break;
+    case 1172:	/* movs */
+    case 1618:	/* orrs */
+      value = 1618;	/* --> orrs.  */
+      break;
+    case 1167:	/* mov */
+    case 1674:	/* sel */
+      value = 1674;	/* --> sel.  */
+      break;
+    case 1170:	/* mov */
+    case 1675:	/* sel */
+      value = 1675;	/* --> sel.  */
+      break;
     default: return NULL;
     }