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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:17 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:17 +0100 |
| commit | 116adc27470ed3682b6236e44e3b18838673036c (patch) | |
| tree | f3d401952aff1a968fb8466cb38b2b6a6d00500d /opcodes/aarch64-asm-2.c | |
| parent | 3bd82c86f0f432bd7653101069bf056fda14b7cd (diff) | |
| download | gdb-116adc27470ed3682b6236e44e3b18838673036c.zip gdb-116adc27470ed3682b6236e44e3b18838673036c.tar.gz gdb-116adc27470ed3682b6236e44e3b18838673036c.tar.bz2 | |
[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
Diffstat (limited to 'opcodes/aarch64-asm-2.c')
| -rw-r--r-- | opcodes/aarch64-asm-2.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index dbfb431..cfd414f 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -647,8 +647,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 189: case 190: case 191: - case 195: - case 198: + case 196: + case 199: return aarch64_ins_regno (self, info, code, inst, errors); case 14: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 201: + case 202: return aarch64_ins_reglane (self, info, code, inst, errors); case 35: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -704,7 +704,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 180: case 181: case 182: - case 200: + case 201: return aarch64_ins_imm (self, info, code, inst, errors); case 43: case 44: @@ -848,11 +848,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 192: case 193: case 194: + case 195: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); - case 196: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 197: - case 199: + return aarch64_ins_sve_index (self, info, code, inst, errors); + case 198: + case 200: return aarch64_ins_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } |