aboutsummaryrefslogtreecommitdiff
path: root/bfd
AgeCommit message (Collapse)AuthorFilesLines
2024-06-24Updated Spanish translations for the bfd and binutils sub-directoriesNick Clifton1-1807/+1270
2024-06-24Automatic date update in version.inGDB Administrator1-1/+1
2024-06-23Automatic date update in version.inGDB Administrator1-1/+1
2024-06-22Automatic date update in version.inGDB Administrator1-1/+1
2024-06-21RISC-V: Remove implicit enablement of Zvknha from Zvkn.Feng Wang1-1/+0
Accroding to the Crypto spec, the Zvkned,Zvknhb,Zvkb and Zvkt are included in the Zvkn. So the Zvknha should be removed from Zvkn. bfd/ChangeLog: * elfxx-riscv.c: Remove zvknha from zvkn.
2024-06-21Automatic date update in version.inGDB Administrator1-1/+1
2024-06-20Revert "Remove LIBINTL_DEP"Alan Modra2-2/+5
This reverts commit e874cbd3879843a83e4bcc4b54cd7107387b1df6. The patch was wrong. LIBINTL_DEP is needed with an in-tree gettext.
2024-06-20Remove LIBINTL_DEPAlan Modra2-5/+2
The intl directory in the source no longer exists. LIBINTL_DEP is thus always empty. Remove references to it. config/ * gettext-sister.m4: Don't AC_SUBST LIBINTL_DEP. bfd/ * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * Makefile.am (*_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. gas/ * Makefile.am (as_new_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. gdb/ * Makefile.in (INTL_DEPS): Don't set or reference. * configure: Regenerate. gdbserver/ * Makefile.in (INTL_DEPS): Don't set or reference. gdbsupport/ * Makefile.in: Regenerate. * configure: Regenerate. gold/ * Makefile.am (deps_var): Remove LIBINTL_DEP. (incremental_dump_DEPENDENCIES, dwp_DEPENDENCIES): Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * testsuite/Makefile.am (DEPENDENCIES): Remove LIBINTL_DEP. * testsuite/Makefile.in: Regenerate. gprof/ * Makefile.am (gprof_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. ld/ * Makefile.am (ld_new_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * configure.ac (BUILD_LIBS): Remove LIBINTL. (BUILD_LIB_DEPS): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate.
2024-06-20LoongArch: TLS IE needs only one dynamic relocXi Ruoyao1-1/+1
As the comment in the code says, TLS_IE needs only one dynamic reloc. But commit b67a17aa7c0c ("LoongArch: Fix the issue of excessive relocation generated by GD and IE") has incorrectly allocated the space for two dynamic relocs, causing libc.so to contain 8 R_LARCH_NONE. Adjust tlsdesc-dso.d for the offset changes and add two tests to ensure there are no R_LARCH_NONE with TLS. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-06-20Automatic date update in version.inGDB Administrator1-1/+1
2024-06-19Automatic date update in version.inGDB Administrator1-1/+1
2024-06-18RISC-V: Fixed typo from smscrind to smcsrind in riscv_implicit_subsets.Nelson Chu1-1/+1
bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Fixed type from smscrind to smcsrind. gas/ * testsuite/gas/riscv/march-imply-smcsrind.d: New testcase. It fails without applying this patch.
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu1-1/+6
Add SiFive cease extension, https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf This aligns LLVM: * https://llvm.org/docs/RISCVUsage.html * https://github.com/llvm/llvm-project/pull/83896 bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'. (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE. (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE. gas/ChangeLog: * doc/c-riscv.texi: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'. * testsuite/gas/riscv/sifive-insns.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask encoding for 'sf.cease'. * opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida1-0/+6
https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0 The Zacas extension introduce compare-and-swap instructions to operate on 32-bit, 64-bit and 128-bit (RV64 only) data values. It introduces three new instructions: - amocas.w (32-bit CAS) - amocas.d (64-bit CAS) - amocas.q (128-bit CAS, RV64 only) Like other AMOs in the A extension, Zacas instructions have '.aq', '.rl' and '.aqrl' variations. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'. (riscv_supported_std_z_ext): Add 'Zacas' extension. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Handle INSN_CLASS_ZACAS case. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zacas-32.d: New test (RV32). * testsuite/gas/riscv/zacas-fail-32.d: Likewise. * testsuite/gas/riscv/zacas-64.d: New test (RV64). * testsuite/gas/riscv/zacas-fail-64.d: Likewise. * testsuite/gas/riscv/zacas.s: New test source. * testsuite/gas/riscv/zacas-fail.s: Likewise. * testsuite/gas/riscv/zacas-fail-32.l: New file. * testsuite/gas/riscv/zacas-fail-64.l: Likewise. include/ChangeLog: * include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition. * include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W) (MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q): Likewise. (amocas_w, amocas_d, amocas_q): Declare instructions. opcodes/ChangeLog: * riscv-opc.c (match_rs2_rd_even): New function. (amocas_w, amocas_d, amocas_q, amocas_w.aq) (amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl) (amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
2024-06-18Automatic date update in version.inGDB Administrator1-1/+1
2024-06-17Error messages emitted during bfd_check_format_matchesAlan Modra1-7/+27
Error/warning messages are only printed for the target that successfully matched, which makes sense for warnings, but not so much for errors where the errors cause no target to match. I noticed this when looking at the pr20520 testcase again with objdump, which just reports "file format not recognized" omitting the five "SHT_GROUP section [index n] has no SHF_GROUP sections" messages. They are omitted because multiple ELF targets match the object file. This is going to be true for all ELF objects due to at least the proper ELF target and the generic ELF target matching. * format.c (print_and_clear_messages): Print messages if all targets with messages have exactly the same set of messages.
2024-06-17Automatic date update in version.inGDB Administrator1-1/+1
2024-06-16Automatic date update in version.inGDB Administrator1-1/+1
2024-06-15Automatic date update in version.inGDB Administrator1-1/+1
2024-06-14x86: Add -z isa-level-report=[none|all|needed|used]H.J. Lu2-11/+119
Add -z isa-level-report=[none|all|needed|used] to the x86 ELF linker to report needed and used x86-64 ISA levels. bfd/ PR ld/31868 * elf-linker-x86.h (elf_x86_isa_level_report): New. (elf_linker_x86_params): Add isa_level_report. * elfxx-x86.c (report_isa_level): New. (_bfd_x86_elf_link_setup_gnu_properties): Check -z isa-level-report=[none|all|needed|used] to report needed and used x86-64 ISA level. ld/ PR ld/31868 * NEWS: Mention -z isa-level-report=[none|all|needed|used]. * ld.texi: Document -z isa-level-report=[none|all|needed|used]. * emulparams/elf32_x86_64.sh: Source x86-64-level-report.sh. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/x86-64-level-report.sh: New file. * testsuite/ld-i386/pr31868a.d: Likewise. * testsuite/ld-i386/pr31868b.d: Likewise. * testsuite/ld-i386/pr31868c.d: Likewise. * testsuite/ld-x86-64/pr31868a-x32.d: Likewise. * testsuite/ld-x86-64/pr31868a.d: Likewise. * testsuite/ld-x86-64/pr31868a.l: Likewise. * testsuite/ld-x86-64/pr31868a.s: Likewise. * testsuite/ld-x86-64/pr31868b-x32.d: Likewise. * testsuite/ld-x86-64/pr31868b.d: Likewise. * testsuite/ld-x86-64/pr31868b.l: Likewise. * testsuite/ld-x86-64/pr31868b.s: Likewise. * testsuite/ld-x86-64/pr31868c-x32.d: Likewise. * testsuite/ld-x86-64/pr31868c.d: Likewise. * testsuite/ld-x86-64/pr31868c.l: Likewise. * testsuite/ld-i386/i386.exp: Run PR ld/31868 tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-06-14Automatic date update in version.inGDB Administrator1-1/+1
2024-06-13Add --rosegment option to BFD linker to stop the '-z separate-code' from ↵Nick Clifton1-1/+3
generating two read-only segments. PR 30907
2024-06-13Automatic date update in version.inGDB Administrator1-1/+1
2024-06-12RISC-V: Support S[sm]csrind extension csrs.Jiawei1-0/+4
This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs. Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs in Smaia/Ssaia extension. bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (enum riscv_csr_class): New extensions. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extensions. include/ChangeLog: * opcode/riscv-opc.h (CSR_MIREG2): New csr. (CSR_MIREG3): Ditto. (CSR_MIREG4): Ditto. (CSR_MIREG5): Ditto. (CSR_MIREG6): Ditto. (CSR_SIREG2): Ditto. (CSR_SIREG3): Ditto. (CSR_SIREG4): Ditto. (CSR_SIREG5): Ditto. (CSR_SIREG6): Ditto. (CSR_VSIREG2): Ditto. (CSR_VSIREG3): Ditto. (CSR_VSIREG4): Ditto. (CSR_VSIREG5): Ditto. (CSR_VSIREG6): Ditto. (DECLARE_CSR): Ditto.
2024-06-12Automatic date update in version.inGDB Administrator1-1/+1
2024-06-11PR31872, Segfault in objdump (elf_slurp_reloc_table_from_section)Alan Modra1-4/+4
This one was triggered by trying to dump an AMDGPU object. elf64-amdgcn.c lacks support for objdump relocation handling. PR 31872 * elfcode.h (elf_slurp_reloc_table_from_section): Don't segfault on NULL elf_info_to_howto_rel.
2024-06-11Automatic date update in version.inGDB Administrator1-1/+1
2024-06-10IBM zSystems: Rewrite l(g)rl @GOTENT to larl for --no-pieIlya Leoshkevich2-12/+6
Regtested on s390x-redhat-linux. Rewriting l(g)rl @GOTENT to larl is unnecessarily guarded by bfd_link_pic(). There were no use cases for this in the past, but since recently the Linux Kernel on s390x is compiled with -fPIE and linked with --no-pie. Remove the unnecessary bfd_link_pic() check. bfd/ChangeLog: * elf32-s390.c (elf_s390_relocate_section): Don't check for bfd_link_pic() when rewriting lrl@GOTENT to larl. (elf_s390_finish_dynamic_symbol): Emit a relative reloc for the above case. * elf64-s390.c (elf_s390_relocate_section): Don't check for bfd_link_pic() when rewriting lgrl@GOTENT to larl. (elf_s390_finish_dynamic_symbol): Emit a relative reloc for the above case. ld/ChangeLog: * testsuite/ld-s390/s390.exp: Hook up the new tests. * testsuite/ld-s390/gotreloc_31-no-pie-1.dd: New test. * testsuite/ld-s390/gotreloc_64-no-pie-1.dd: New test.
2024-06-10PR31873, buffer overflow in evax_bfd_print_dstAlan Modra1-0/+2
PR 31873 * vms-alpha.c (evax_bfd_print_dst): Sanity check len against dst_size.
2024-06-10Automatic date update in version.inGDB Administrator1-1/+1
2024-06-10autoupdate: regen after replacing obsolete macrosMatthieu Longo1-4/+2
2024-06-10autoupdate: add square brackets around arguments of AC_INITMatthieu Longo1-1/+1
https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fINIT-2
2024-06-10autoupdate: replace obsolete macros AC_AIX, AC_MINIX, and AC_GNU_SOURCEMatthieu Longo1-1/+0
- AC_AIX, AC_MINIX, and AC_GNU_SOURCE by AC_USE_SYSTEM_EXTENSIONS https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fAIX https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fMINIX-1 https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fGNU_005fSOURCE-1
2024-06-09Automatic date update in version.inGDB Administrator1-1/+1
2024-06-08Automatic date update in version.inGDB Administrator1-1/+1
2024-06-07Re: Yet another ecoff fuzzed object fixAlan Modra1-0/+1
In commit 6fc018e9e593 I replaced the fdr_ptr csym check against the header isymMax count with a check against bfd symcount. In fact, both checks are needed. The isymMax check sanity checks accesses against the external sym array, the symcount one against the internal array. * ecoff.c (_bfd_ecoff_slurp_symbol_table): Reinstate fdr_ptr csym check against isymMax.
2024-06-07aarch64: Fix DT_RELR support with discarded sectionsSzabolcs Nagy1-2/+3
In case of discarded sections, via /DISCARD/ or .gnu.linkonce, relr relocation accounting was wrong. This broke building linux. The issue was that the *_relocate_section logic was copied to record_relr_non_got_relocs to find the relative relocs that can be packed, however *_relocate_section is not called on sections that are discarded, while record_relr_non_got_relocs is called for all input sections. The fix is to filter out the discarded sections with the same logic that is used to count non-GOT relocs in *_late_size_sections for local symbols earlier. Use the discarded_section helper in both cases to clarify the intent and handle all corner-cases consistently. GOT relocations are affected too if all sections are discarded that reference the GOT entry of a particular symbol, however this can cause unused GOT entries independently of DT_RELR, and the only difference with DT_RELR is that a relative reloc may be emitted instead of a R_AARCH64_NONE for the unused GOT entry which is acceptable. A proper fix would require redoing the GOT refcounting after we know the discarded sections, see bug 31850.
2024-06-07Automatic date update in version.inGDB Administrator1-1/+1
2024-06-06Updated Spanish translation for the bfd/ directoryNick Clifton1-852/+536
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng1-0/+7
This implements the Zvfbfwma extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add> 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin 2 Depending on different usage scenarios, the Zvfbfwma extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. This is consistent with the processing strategy in Zvfbfmin. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfwma.d: New test. * testsuite/gas/riscv/zvfbfwma.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define. (MASK_VFWMACCBF16_VF): Ditto. (MATCH_VFWMACCBF16_VV): Ditto. (MASK_VFWMACCBF16_VV): Ditto. (DECLARE_INSN): New declarations for Zvfbfwma. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFWMA opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfwma instructions.
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng1-0/+6
This implements the Zvfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts> Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfmin.d: New test. * testsuite/gas/riscv/zvfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define. (MASK_VFNCVTBF16_F_F_W): Ditto. (MATCH_VFWCVTBF16_F_F_V): Ditto. (MASK_VFWCVTBF16_F_F_V): Ditto. (DECLARE_INSN): New declarations for Zvfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFMIN opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfmin instructions.
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng1-0/+6
This implements the Zfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc> 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. 5 For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zfbfmin.d: New test. * testsuite/gas/riscv/zfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. (MASK_FCVT_BF16_S): Ditto. (MATCH_FCVT_S_BF16): Ditto. (MASK_FCVT_S_BF16): Ditto. (DECLARE_INSN): New declarations for Zfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c: Add Zfbfmin instructions.
2024-06-06Automatic date update in version.inGDB Administrator1-1/+1
2024-06-05Fix illegal memory access when bfd_get_section_contents is called with a ↵Nick Clifton1-10/+34
NULL section pointer. PR 31843
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVmem as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mem-fail-march.d: New test. * testsuite/gas/riscv/cv-mem-fail-march.l: New test. * testsuite/gas/riscv/cv-mem-fail-march.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-mem-lbpost.d: New test. * testsuite/gas/riscv/cv-mem-lbpost.s: New test. * testsuite/gas/riscv/cv-mem-lbrr.d: New test. * testsuite/gas/riscv/cv-mem-lbrr.s: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lbupost.d: New test. * testsuite/gas/riscv/cv-mem-lbupost.s: New test. * testsuite/gas/riscv/cv-mem-lburr.d: New test. * testsuite/gas/riscv/cv-mem-lburr.s: New test. * testsuite/gas/riscv/cv-mem-lburrpost.d: New test. * testsuite/gas/riscv/cv-mem-lburrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhpost.d: New test. * testsuite/gas/riscv/cv-mem-lhpost.s: New test. * testsuite/gas/riscv/cv-mem-lhrr.d: New test. * testsuite/gas/riscv/cv-mem-lhrr.s: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhupost.d: New test. * testsuite/gas/riscv/cv-mem-lhupost.s: New test. * testsuite/gas/riscv/cv-mem-lhurr.d: New test. * testsuite/gas/riscv/cv-mem-lhurr.s: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.s: New test. * testsuite/gas/riscv/cv-mem-lwpost.d: New test. * testsuite/gas/riscv/cv-mem-lwpost.s: New test. * testsuite/gas/riscv/cv-mem-lwrr.d: New test. * testsuite/gas/riscv/cv-mem-lwrr.s: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.s: New test. * testsuite/gas/riscv/cv-mem-sbpost.d: New test. * testsuite/gas/riscv/cv-mem-sbpost.s: New test. * testsuite/gas/riscv/cv-mem-sbrr.d: New test. * testsuite/gas/riscv/cv-mem-sbrr.s: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-shpost.d: New test. * testsuite/gas/riscv/cv-mem-shpost.s: New test. * testsuite/gas/riscv/cv-mem-shrr.d: New test. * testsuite/gas/riscv/cv-mem-shrr.s: New test. * testsuite/gas/riscv/cv-mem-shrrpost.d: New test. * testsuite/gas/riscv/cv-mem-shrrpost.s: New test. * testsuite/gas/riscv/cv-mem-swpost.d: New test. * testsuite/gas/riscv/cv-mem-swpost.s: New test. * testsuite/gas/riscv/cv-mem-swrr.d: New test. * testsuite/gas/riscv/cv-mem-swrr.s: New test. * testsuite/gas/riscv/cv-mem-swrrpost.d: New test. * testsuite/gas/riscv/cv-mem-swrrpost.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvmem string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVmem. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVmem. (enum riscv_insn_class): Add the XCVmem instruction class. opcodes/ChangeLog: * riscv-opc.c: Add XCVmem instructions.
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> Nazareno Bruschi <nazareno.bruschi@embecosm.com> Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions.
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVelw as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-elw-fail.d: New test. * testsuite/gas/riscv/cv-elw-fail.l: New test. * testsuite/gas/riscv/cv-elw-fail.s: New test. * testsuite/gas/riscv/cv-elw-fail-march.d: New test. * testsuite/gas/riscv/cv-elw-fail-march.l: New test. * testsuite/gas/riscv/cv-elw-fail-march.s: New test. * testsuite/gas/riscv/cv-elw-pass.d: New test. * testsuite/gas/riscv/cv-elw-pass.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvelw string. opcodes/ChangeLog: * riscv-opc.c: (riscv_opcode) Add event load instructions. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction opcode macros. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
2024-06-05Automatic date update in version.inGDB Administrator1-1/+1
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang4-29/+1
R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only created at the first time to handle alignment directive. This means that all other sections may use this symbol. If the section of this symbol is discarded, there may be problems. Search it in its own section. Remove elf_backend_data.is_rela_normal() function added at commit daeda14191c. Co-authored-by: Jinyang He <hejinyang@loongson.cn> Reported-by: WANG Xuerui <git@xen0n.name> Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t
2024-06-04Automatic date update in version.inGDB Administrator1-1/+1
generated by cgit v1.1 at 2024-11-18 14:04:12 +0000