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| author | Mary Bennett <mary.bennett682@gmail.com> | 2024-05-30 16:06:57 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-05 18:09:09 +0800 |
| commit | 940da069b48980ce957dd4cc010a9a41e05d1553 (patch) | |
| tree | b259f1aeefe9dcafcb45ee0d8497602aa288b03a /bfd | |
| parent | f95540d91f4c3df373c0f9e212030154658d7f6f (diff) | |
| download | gdb-940da069b48980ce957dd4cc010a9a41e05d1553.zip gdb-940da069b48980ce957dd4cc010a9a41e05d1553.tar.gz gdb-940da069b48980ce957dd4cc010a9a41e05d1553.tar.bz2 | |
RISC-V: Add support for XCVelw extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction
class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XCVelw as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-elw-fail.d: New test.
* testsuite/gas/riscv/cv-elw-fail.l: New test.
* testsuite/gas/riscv/cv-elw-fail.s: New test.
* testsuite/gas/riscv/cv-elw-fail-march.d: New test.
* testsuite/gas/riscv/cv-elw-fail-march.l: New test.
* testsuite/gas/riscv/cv-elw-fail-march.s: New test.
* testsuite/gas/riscv/cv-elw-pass.d: New test.
* testsuite/gas/riscv/cv-elw-pass.s: New test.
* testsuite/gas/riscv/march-help.l: Add xcvelw string.
opcodes/ChangeLog:
* riscv-opc.c: (riscv_opcode) Add event load instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
instruction opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index dfacb87..4750dfc 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1454,6 +1454,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = { {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2674,6 +2675,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xcvmac"); case INSN_CLASS_XCVALU: return riscv_subset_supports (rps, "xcvalu"); + case INSN_CLASS_XCVELW: + return riscv_subset_supports (rps, "xcvelw"); case INSN_CLASS_XTHEADBA: return riscv_subset_supports (rps, "xtheadba"); case INSN_CLASS_XTHEADBB: @@ -2932,6 +2935,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xcvmac"; case INSN_CLASS_XCVALU: return "xcvalu"; + case INSN_CLASS_XCVELW: + return "xcvelw"; case INSN_CLASS_XTHEADBA: return "xtheadba"; case INSN_CLASS_XTHEADBB: |