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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2024-06-06 15:59:52 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-06 16:10:51 +0800 |
| commit | d9c14a8744b01b0d3d03a661c732a4d4d5740fbc (patch) | |
| tree | 104016466320290c6444f5b089e737449cf23f7d /bfd | |
| parent | af38c6367ff0c6af1639b389eb34cf9983c30ff5 (diff) | |
| download | gdb-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.zip gdb-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.tar.gz gdb-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.tar.bz2 | |
RISC-V: Add support for Zvfbfmin extension
This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>
Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfmin.d: New test.
* testsuite/gas/riscv/zvfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
(MASK_VFNCVTBF16_F_F_W): Ditto.
(MATCH_VFWCVTBF16_F_F_V): Ditto.
(MASK_VFWCVTBF16_F_F_V): Ditto.
(DECLARE_INSN): New declarations for Zvfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFMIN
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfmin instructions.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 1d70139..0131ce8 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, {"zabha", "a", check_implicit_always}, + {"zvfbfmin", "zve32f", check_implicit_always}, {"zvfh", "zvfhmin", check_implicit_always}, {"zvfh", "zfhmin", check_implicit_always}, {"zvfhmin", "zve32f", check_implicit_always}, @@ -1393,6 +1394,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2647,6 +2649,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVFBFMIN: + return riscv_subset_supports (rps, "zvfbfmin"); case INSN_CLASS_ZVKB: return riscv_subset_supports (rps, "zvkb"); case INSN_CLASS_ZVKG: @@ -2917,6 +2921,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVBC: return _("zvbc"); + case INSN_CLASS_ZVFBFMIN: + return "zvfbfmin"; case INSN_CLASS_ZVKB: return _("zvkb"); case INSN_CLASS_ZVKG: |