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3 hoursRISC-V: Add platform property/capability extensionsTsukasa OI1-0/+33
RISC-V Profiles document defines number of "extensions" that indicate certain platform properties/capabilities just like 'Zkt' extension from the RISC-V cryptography extensions. This commit defines 20 platform property/capability extensions as defined in the RISC-V Profiles documentation. The only exception: 'Ssstateen' extension is defined separately because it defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. This is based on the ratified version of RISC-V Profiles: <https://github.com/riscv/riscv-profiles/releases/tag/v1.0> [Definition] "Main memory regions": Main memory regions (in contrast to I/O or vacant memory regions) with both the cacheability and coherence PMAs. [New Unprivileged Extensions] 1. 'Ziccif' "Main memory regions" support instruction fetch and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) are atomic. 2. 'Ziccrse' "Main memory regions" provide the eventual success guarantee for LR/SC sequence (RsrvEventual). 3. 'Ziccamoa' "Main memory regions" support all currently-defined AMO operations including swap, logical and arithmetic operations (AMOArithmetic). 4. 'Za64rs' For LR/SC instructions, reservation sets are contiguous, naturally aligned and at most 64-bytes in size. 5. 'Za128rs' Likewise, but reservation sets are at most 128-bytes in size. 6. 'Zicclsm' Misaligned loads / stores to "main memory regions" are supported. Those include both regular scalar and vector accesses but does not include AMOs and other specialized forms of memory accesses. 7. 'Zic64b' Cache blocks are (exactly) 64-bytes in size and naturally aligned. [New Privileged Extensions] 1. 'Svbare' "satp" mode Bare is supported. 2. 'Svade' Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear. 3. 'Ssccptr' "Main memory regions" support hardware page-table reads. 4. 'Sstvecd' "stvec" mode Direct is supported. When "stvec" mode is Direct, "stvec.BASE" is capable of holding any valid 4-byte aligned address. 5. 'Sstvala' "stval" is always written with a nonzero value whenever possible as specified in the Privileged Architecture documentation (version 20211203: see section 4.1.9). 6. 'Sscounterenw' For any "hpmcounter" that is not read-only zero, the corresponding bit in "scounteren" is writable. 7. 'Ssu64xl' "sstatus.UXL" is capable of holding the value 0b10 (UXLEN==64 is supported). 8. 'Shcounterenw' Similar to 'Sscounterenw' but the same rule applies to "hcounteren". 9. 'Shvstvala' Similar to 'Sstvala' but the same rule applies to "vstval". 10. 'Shtvala' "htval" is written with the faulting guest physical address as long as permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). 11. 'Shvstvecd' Similar to 'Sstvecd' but the same rule applies to "vstvec". 12. 'Shvsatpa' All translation modes supported in "satp" are also supported in "vsatp". 13. 'Shgatpa' For each supported virtual memory scheme SvNN supported in "satp", the corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare is also supported. [Implications] (Due to reservation set size constraints) - 'Za64rs' -> 'Za128rs' (Due to the fact that a privileged "extension" directly refers a CSR) - 'Svbare' -> 'Zicsr' - 'Sstvecd' -> 'Zicsr' - 'Sstvala' -> 'Zicsr' - 'Sscounterenw' -> 'Zicsr' - 'Ssu64xl' -> 'Zicsr' (Due to the fact that a privileged "extension" indirectly depends on CSRs) - 'Svade' -> 'Zicsr' (Due to the fact that a privileged "extension" is a hypervisor property) - 'Shcounterenw' -> 'H' - 'Shvstvala' -> 'H' - 'Shtvala' -> 'H' - 'Shvstvecd' -> 'H' - 'Shvsatpa' -> 'H' - 'Shgatpa' -> 'H' bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Updated for property and capability extensions. (riscv_supported_std_z_ext): Added zic64b, ziccamoa, ziccif, zicclsm, ziccrse, za64rs and za128rs extensions. (riscv_supported_std_s_ext): Added shcounterenw, shgatpa, shtvala, shvsatpa, shvstvala, shvstvecd, ssccptr, sscounterenw, sstvala, sstvecd, ssu64xlm svade and svbare extensions. gas/ * testsuite/gas/riscv/imply.d: Updated for property and capability extensions. * testsuite/gas/riscv/imply.s: Likewise. * testsuite/gas/riscv/march-help.l: Likewse.
7 hoursLoongArch: Not alloc dynamic relocs if symbol is absoluteJinyang He1-7/+7
The absolute symbol should be resolved to const when link to dso or exe. Alloc dynamic relocs will cause extra space and R_LARCH_NONE finally.
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35 hourself: Add glibc version dependency only if neededH.J. Lu1-9/+23
There is no need to add a needed glibc version if the glibc base version includes the needed glibc version. PR ld/31966 * elflink.c (elf_link_add_glibc_verneed): Add glibc_minor_base. Skip if the glibc base version includes the needed glibc version. (_bfd_elf_link_add_glibc_version_dependency): Initialize glibc_minor_base to INT_MAX and pass it to elf_link_add_glibc_verneed. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
48 hoursLTO: Properly check wrapper symbolH.J. Lu1-0/+2
Add wrapper_symbol to bfd_link_hash_entry and set it to true for wrapper symbol. Set wrap_status to wrapper if wrapper_symbol is true in LTO. Note: Calling unwrap_hash_lookup to check for the wrapper symbol works only when there is a definition for the wrapped symbol since references to the wrapped symbol have been redirected to the wrapper symbol. bfd/ PR ld/31956 * linker.c (bfd_wrapped_link_hash_lookup): Set wrapper_symbol for wrapper symbol. include/ PR ld/31956 * bfdlink.h (bfd_link_hash_entry): Add wrapper_symbol. ld/ PR ld/31956 * plugin.c (get_symbols): Set wrap_status to wrapper if wrapper_symbol is set. * testsuite/ld-plugin/lto.exp: Run PR ld/31956 tests. * testsuite/ld-plugin/pr31956a.c: New file. * testsuite/ld-plugin/pr31956b.c: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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6 daysLoongArch: Add DT_RELR supportXi Ruoyao1-4/+484
The logic is same as a71d87680110 ("aarch64: Add DT_RELR support"). As LoongArch does not have -z dynamic-undefined-weak, we don't need to consider UNDEFWEAK_NO_DYNAMIC_RELOC. The linker relaxation adds another layer of complexity. When we delete bytes in a section during relaxation, we need to fix up the offset in the to-be-packed relative relocations against this section. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
6 daysLoongArch: Make protected function symbols local for -sharedXi Ruoyao1-20/+56
On LoongArch there is no reason to treat STV_PROTECTED STT_FUNC symbols as preemptible. See the comment above LARCH_REF_LOCAL for detailed explanation. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
6 daysLoongArch: Fix bad reloc with mixed visibility ifunc symbols in shared librariesXi Ruoyao1-12/+65
With a simple test case: .globl ifunc .globl ifunc_hidden .hidden ifunc_hidden .type ifunc, %gnu_indirect_function .type ifunc_hidden, %gnu_indirect_function .text .align 2 ifunc: ret ifunc_hidden: ret test: bl ifunc bl ifunc_hidden "ld -shared" produces a shared object with one R_LARCH_NONE (instead of R_LARCH_JUMP_SLOT as we expect) to relocate the GOT entry of "ifunc". It's because the indices in .plt and .rela.plt mismatches for STV_DEFAULT STT_IFUNC symbols when another PLT entry exists for a STV_HIDDEN STT_IFUNC symbol, and such a mismatch breaks the logic of loongarch_elf_finish_dynamic_symbol. Fix the issue by reordering .plt so the indices no longer mismatch. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
6 daysLoongArch: Reject R_LARCH_32 from becoming a runtime reloc in ELFCLASS64Xi Ruoyao1-2/+28
We were converting R_LARCH_32 to R_LARCH_RELATIVE for ELFCLASS64: $ cat t.s .data x: .4byte x .4byte 0xdeadbeef $ as/as-new t.s -o t.o $ ld/ld-new -shared t.o $ objdump -R a.out: file format elf64-loongarch DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE 00000000000001a8 R_LARCH_RELATIVE *ABS*+0x00000000000001a8 But this is just wrong: at runtime the dynamic linker will run *(uintptr *)&x += load_address, clobbering the next 4 bytes of data ("0xdeadbeef" in the example). If we keep the R_LARCH_32 reloc as-is in ELFCLASS64, it'll be rejected by the Glibc dynamic linker anyway. And it does not make too much sense to modify Glibc to support it. So we can just reject it like x86_64: relocation R_X86_64_32 against `.data' can not be used when making a shared object; recompile with -fPIC or RISC-V: relocation R_RISCV_32 against non-absolute symbol `a local symbol' can not be used in RV64 when making a shared object Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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11 daystweak latest vms-alpha.c changeAlan Modra1-1/+1
It's that tiny bit nicer to have the "len" expression in order of the components in the buffer.
11 daysRe: Rewrite SHT_GROUP handlingAlan Modra1-50/+52
Some more error tweaks. Report a zero entry as "invalid entry.." rather than "unknown type..", and allow a section to be mentioned twice in a group. * elf.c (process_sht_group_entries): Tweak error messages, and allow a duplicate index in a group without reporting an error.
11 daysAutomatic date update in version.inGDB Administrator1-1/+1
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13 daysLoongArch: Do not check R_LARCH_SOP_PUSH_ABSOLUTE to avoid broken links to ↵Lulu Cai1-5/+6
old object files R_LARCH_SOP_PUSH_ABSOLUTE with -fPIC was heavily used in the era of gas-2.38. We do not check this relocation to prevent broken links with old object files.
13 daysRISC-V: Shrink the riscv_implicit_subsets table.Nelson Chu1-165/+149
Allow to add implicit extensions by using the syntax of `.option arch, +-', so that the table is shrinked and more readable. bfd/ * elfxx-riscv.c (check_implicit_always): Removed the unused IMPLICIT parameter. (check_implicit_for_i): Likewise. (riscv_implicit_subsets): Shrink the table by allowing the syntax of `.option arch, +-' for implicit extensions. (riscv_update_subset1): New function, called from riscv_update_subset or riscv_parse_add_implicit_subsets. It basically does the same thing as riscv_update_subset function before. (riscv_parse_add_implicit_subsets): Updated. (riscv_update_subset): Updated.
13 daysRISC-V: PR27180, Update relocation for riscv_zero_pcrel_hi_reloc.Nelson Chu1-12/+40
When pcrel access overflow, the riscv_zero_pcrel_hi_reloc may convert pcrel relocation to absolutly access if possible at the relocate stage. We used to encode the target address into r_sym of R_RISCV_HI20 if it is converted from R_RISCV_PCREL_HI20. But that may cause segfault if --emit-relocs is set, since r_sym becomes an address rather than a symbol index. Although the relocate result is correct, it does not meet the definition, so may cause unexpected behaviors. This patch encodes the target address into r_addend, rather than r_sym, if riscv_zero_pcrel_hi_reloc converts the relocation. Besdies, since the corresponding pcrel_lo relocation are also changed to absolutly access, we should also update them to R_RISCV_LO12_I/S. bfd/ PR 27180 * elfnn-riscv.c (riscv_pcrel_hi_reloc): New boolean `absolute', to inform corresponding pcrel_lo that the pcrel_hi relocation was already converted to hi20 relocation. (riscv_record_pcrel_hi_reloc): Likewise, record `absolute'. (riscv_pcrel_lo_reloc): Removed `const' for Elf_Internal_Rela *reloc, since we may need to convert it from pcrel_lo to lo relocation. (riscv_record_pcrel_lo_reloc): Likewise. Convert pcrel_lo to lo relocation if corresponding pcrel_hi was converted to hi relocation. (riscv_zero_pcrel_hi_reloc): Encode target absolute address into r_addend rather than r_sym. Clear the `addr' to avoid duplicate relocate in the perform_relocation. (riscv_elf_relocate_section): Updated. ld/ PR 27180 * testsuite/ld-riscv-elf/pcrel-lo-addend-3a-emit-relocs.d: New testcase. Segfault without applying this patch. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
13 daysRISC-V: Add Zabha extension CAS instructions.Jiawei1-0/+3
This patch update the cas instruction in Zabha extension [1], when both Zabha and Zacas extension enabled. [1] https://github.com/riscv/riscv-zabha/tags bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension case. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New instructions. * testsuite/gas/riscv/zabha.d: Ditto. * testsuite/gas/riscv/zabha.s: Ditto. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes. (MASK_AMOCAS_B): Ditto. (MATCH_AMOCAS_H): Ditto. (MASK_AMOCAS_H): Ditto. (DECLARE_INSN): New instructions. * opcode/riscv.h (enum riscv_insn_class): New class case. opcodes/ChangeLog: * riscv-opc.c: New instructions.
13 daysAutomatic date update in version.inGDB Administrator1-1/+1
2024-06-27Re: Rewrite SHT_GROUP handlingAlan Modra1-34/+15
There is no need to loop over the headers twice. Remove that leftover from the previous scheme. Also, the previous scheme silently ignored a section being mentioned in two or more SHT_GROUP sections. * elf.c (process_sht_group_entries): Prevent sections from belonging to two groups. (_bfd_elf_setup_sections): Process groups in a single loop over headers.
2024-06-27Automatic date update in version.inGDB Administrator1-1/+1
2024-06-27Rewrite SHT_GROUP handlingAlan Modra2-287/+108
This patch delays setting up elf_next_in_group, elf_sec_group and elf_group_name when reading ELF object files until after all ELF sections have been processed by bfd_section_from_shdr. This is simpler and more robust than the current scheme of driving the whole process on detecting a section with SHF_GROUP set. * elf-bfd.h (struct elf_obj_tdata): Delete group_sect_ptr, num_group and group_search_offset. * elf.c (Elf_Internal_Group): Delete. (setup_group): Delete function. (IS_VALID_GROUP_SECTION_HEADER): Delete macro. (is_valid_group_section_header), (process_sht_group_entries): New functions. (_bfd_elf_setup_sections): Handle group sections here.. (_bfd_elf_make_section_from_shdr): ..rather than here. (bfd_section_from_shdr): Don't check SHT_GROUP validity here.
2024-06-26Automatic date update in version.inGDB Administrator1-1/+1
2024-06-25Updated Russian translation for the bfd/ sub-directoryNick Clifton1-1247/+1418
2024-06-25Fix calculation of space remaining in buffer when printing the contents of a ↵Nick Clifton1-2/+5
DST__K_RECBEG type debug symbol for the VMS Alpha port. PR 31873
2024-06-25aarch64: Add DT_RELR support for ILP32 ABISzabolcs Nagy1-16/+21
Extend the 64bit DT_RELR support to work on 32bit ELF too. For this only a few changes were needed in the sizing and creation of the relr relocations.
2024-06-25Automatic date update in version.inGDB Administrator1-1/+1
2024-06-24Updated Spanish translations for the bfd and binutils sub-directoriesNick Clifton1-1807/+1270
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2024-06-21RISC-V: Remove implicit enablement of Zvknha from Zvkn.Feng Wang1-1/+0
Accroding to the Crypto spec, the Zvkned,Zvknhb,Zvkb and Zvkt are included in the Zvkn. So the Zvknha should be removed from Zvkn. bfd/ChangeLog: * elfxx-riscv.c: Remove zvknha from zvkn.
2024-06-21Automatic date update in version.inGDB Administrator1-1/+1
2024-06-20Revert "Remove LIBINTL_DEP"Alan Modra2-2/+5
This reverts commit e874cbd3879843a83e4bcc4b54cd7107387b1df6. The patch was wrong. LIBINTL_DEP is needed with an in-tree gettext.
2024-06-20Remove LIBINTL_DEPAlan Modra2-5/+2
The intl directory in the source no longer exists. LIBINTL_DEP is thus always empty. Remove references to it. config/ * gettext-sister.m4: Don't AC_SUBST LIBINTL_DEP. bfd/ * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * Makefile.am (*_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. gas/ * Makefile.am (as_new_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. gdb/ * Makefile.in (INTL_DEPS): Don't set or reference. * configure: Regenerate. gdbserver/ * Makefile.in (INTL_DEPS): Don't set or reference. gdbsupport/ * Makefile.in: Regenerate. * configure: Regenerate. gold/ * Makefile.am (deps_var): Remove LIBINTL_DEP. (incremental_dump_DEPENDENCIES, dwp_DEPENDENCIES): Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * testsuite/Makefile.am (DEPENDENCIES): Remove LIBINTL_DEP. * testsuite/Makefile.in: Regenerate. gprof/ * Makefile.am (gprof_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. ld/ * Makefile.am (ld_new_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * configure.ac (BUILD_LIBS): Remove LIBINTL. (BUILD_LIB_DEPS): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate.
2024-06-20LoongArch: TLS IE needs only one dynamic relocXi Ruoyao1-1/+1
As the comment in the code says, TLS_IE needs only one dynamic reloc. But commit b67a17aa7c0c ("LoongArch: Fix the issue of excessive relocation generated by GD and IE") has incorrectly allocated the space for two dynamic relocs, causing libc.so to contain 8 R_LARCH_NONE. Adjust tlsdesc-dso.d for the offset changes and add two tests to ensure there are no R_LARCH_NONE with TLS. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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2024-06-19Automatic date update in version.inGDB Administrator1-1/+1
2024-06-18RISC-V: Fixed typo from smscrind to smcsrind in riscv_implicit_subsets.Nelson Chu1-1/+1
bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Fixed type from smscrind to smcsrind. gas/ * testsuite/gas/riscv/march-imply-smcsrind.d: New testcase. It fails without applying this patch.
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu1-1/+6
Add SiFive cease extension, https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf This aligns LLVM: * https://llvm.org/docs/RISCVUsage.html * https://github.com/llvm/llvm-project/pull/83896 bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'. (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE. (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE. gas/ChangeLog: * doc/c-riscv.texi: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'. * testsuite/gas/riscv/sifive-insns.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask encoding for 'sf.cease'. * opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida1-0/+6
https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0 The Zacas extension introduce compare-and-swap instructions to operate on 32-bit, 64-bit and 128-bit (RV64 only) data values. It introduces three new instructions: - amocas.w (32-bit CAS) - amocas.d (64-bit CAS) - amocas.q (128-bit CAS, RV64 only) Like other AMOs in the A extension, Zacas instructions have '.aq', '.rl' and '.aqrl' variations. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'. (riscv_supported_std_z_ext): Add 'Zacas' extension. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Handle INSN_CLASS_ZACAS case. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zacas-32.d: New test (RV32). * testsuite/gas/riscv/zacas-fail-32.d: Likewise. * testsuite/gas/riscv/zacas-64.d: New test (RV64). * testsuite/gas/riscv/zacas-fail-64.d: Likewise. * testsuite/gas/riscv/zacas.s: New test source. * testsuite/gas/riscv/zacas-fail.s: Likewise. * testsuite/gas/riscv/zacas-fail-32.l: New file. * testsuite/gas/riscv/zacas-fail-64.l: Likewise. include/ChangeLog: * include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition. * include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W) (MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q): Likewise. (amocas_w, amocas_d, amocas_q): Declare instructions. opcodes/ChangeLog: * riscv-opc.c (match_rs2_rd_even): New function. (amocas_w, amocas_d, amocas_q, amocas_w.aq) (amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl) (amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
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