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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2024-06-06 15:59:53 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-06 16:10:53 +0800 |
| commit | 0b4595be3f04aa3741157b24654e554fc3264fc2 (patch) | |
| tree | 777105142cf7f51e06a3a0ec62d8ffd6dbcb8b96 /bfd | |
| parent | d9c14a8744b01b0d3d03a661c732a4d4d5740fbc (diff) | |
| download | gdb-0b4595be3f04aa3741157b24654e554fc3264fc2.zip gdb-0b4595be3f04aa3741157b24654e554fc3264fc2.tar.gz gdb-0b4595be3f04aa3741157b24654e554fc3264fc2.tar.bz2 | |
RISC-V: Add support for Zvfbfwma extension
This implements the Zvfbfwma extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add>
1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension."
1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin
2 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfwma.d: New test.
* testsuite/gas/riscv/zvfbfwma.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define.
(MASK_VFWMACCBF16_VF): Ditto.
(MATCH_VFWMACCBF16_VV): Ditto.
(MASK_VFWMACCBF16_VV): Ditto.
(DECLARE_INSN): New declarations for Zvfbfwma.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFWMA
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfwma instructions.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0131ce8..1fe7e5d 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1193,6 +1193,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "zvl128b", check_implicit_always}, {"zabha", "a", check_implicit_always}, {"zvfbfmin", "zve32f", check_implicit_always}, + {"zvfbfwma", "zve32f", check_implicit_always}, + {"zvfbfwma", "zfbfmin", check_implicit_always}, {"zvfh", "zvfhmin", check_implicit_always}, {"zvfh", "zfhmin", check_implicit_always}, {"zvfhmin", "zve32f", check_implicit_always}, @@ -1395,6 +1397,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfwma", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2651,6 +2654,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbc"); case INSN_CLASS_ZVFBFMIN: return riscv_subset_supports (rps, "zvfbfmin"); + case INSN_CLASS_ZVFBFWMA: + return riscv_subset_supports (rps, "zvfbfwma"); case INSN_CLASS_ZVKB: return riscv_subset_supports (rps, "zvkb"); case INSN_CLASS_ZVKG: @@ -2923,6 +2928,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbc"); case INSN_CLASS_ZVFBFMIN: return "zvfbfmin"; + case INSN_CLASS_ZVFBFWMA: + return "zvfbfwma"; case INSN_CLASS_ZVKB: return _("zvkb"); case INSN_CLASS_ZVKG: |