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| author | Mary Bennett <mary.bennett682@gmail.com> | 2024-05-30 16:06:58 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-05 18:09:22 +0800 |
| commit | b0f266f38b49c516ab0f95c638720073899446cc (patch) | |
| tree | 1df960ffed13965cfc1272737d202f455ed56d64 /bfd | |
| parent | 940da069b48980ce957dd4cc010a9a41e05d1553 (diff) | |
| download | gdb-b0f266f38b49c516ab0f95c638720073899446cc.zip gdb-b0f266f38b49c516ab0f95c638720073899446cc.tar.gz gdb-b0f266f38b49c516ab0f95c638720073899446cc.tar.bz2 | |
RISC-V: Add support for XCVbi extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
Nazareno Bruschi <nazareno.bruschi@embecosm.com>
Lin Sinan
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
macros for XCVbi.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVbi.
(enum riscv_insn_class): Add the XCVbi instruction class.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Note XCVbi as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-bi-beqimm.d: New test.
* testsuite/gas/riscv/cv-bi-beqimm.s: New test.
* testsuite/gas/riscv/cv-bi-bneimm.d: New test.
* testsuite/gas/riscv/cv-bi-bneimm.s: New test.
* testsuite/gas/riscv/cv-bi-fail-march.d: New test.
* testsuite/gas/riscv/cv-bi-fail-march.l: New test.
* testsuite/gas/riscv/cv-bi-fail-march.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.
* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.
* testsuite/gas/riscv/march-help.l: Add xcvbi string.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK
macros for XCVbi.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVbi.
(enum riscv_insn_class): Add the XCVbi instruction class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add disassembly for new operand.
* riscv-opc.c: Add XCVbi instructions.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 4750dfc..c96d502 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1455,6 +1455,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2677,6 +2678,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xcvalu"); case INSN_CLASS_XCVELW: return riscv_subset_supports (rps, "xcvelw"); + case INSN_CLASS_XCVBI: + return riscv_subset_supports (rps, "xcvbi"); case INSN_CLASS_XTHEADBA: return riscv_subset_supports (rps, "xtheadba"); case INSN_CLASS_XTHEADBB: @@ -2937,6 +2940,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xcvalu"; case INSN_CLASS_XCVELW: return "xcvelw"; + case INSN_CLASS_XCVBI: + return "xcvbi"; case INSN_CLASS_XTHEADBA: return "xtheadba"; case INSN_CLASS_XTHEADBB: |