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2011-10-06system.h (OUTPUT_ADDR_CONST_EXTRA): Poison.Anatoly Sokolov2-24/+0
* system.h (OUTPUT_ADDR_CONST_EXTRA): Poison. * doc/tm.texi.in (OUTPUT_ADDR_CONST_EXTRA): Remove documentation. * doc/tm.texi: Regenerate. * target.def (output_addr_const_extra): Use hook_bool_FILEptr_rtx_false. * targhooks.c (default_asm_output_addr_const_extra): Remove. * targhooks.h (default_asm_output_addr_const_extra): Remove. * hooks.c (hook_bool_FILEptr_rtx_false): New functions. * hooks.h (hook_bool_FILEptr_rtx_false): Declare. From-SVN: r179630
2011-10-06i386.opt (recip_mask, [...]): New variables and cl_target member.Michael Matz1-1/+19
* i386/i386.opt (recip_mask, recip_mask_explicit, x_recip_mask_explicit): New variables and cl_target member. (mrecip=): New option. * i386/i386.h (RECIP_MASK_DIV, RECIP_MASK_SQRT, RECIP_MASK_VEC_DIV, RECIP_MASK_VEC_SQRT, RECIP_MASK_ALL, RECIP_MASK_NONE): New bitmasks. (TARGET_RECIP_DIV, TARGET_RECIP_SQRT, TARGET_RECIP_VEC_DIV, TARGET_RECIP_VEC_SQRT): New tests. * i386/i386.md (divsf3): Check TARGET_RECIP_DIV. (sqrt<mode>2): Check TARGET_RECIP_SQRT. * i386/sse.md (div<mode>3): Check TARGET_RECIP_VEC_DIV. (sqrt<mode>2): Check TARGET_RECIP_VEC_SQRT. * i386/i386.c (ix86_option_override_internal): Set recip_mask for -mrecip and -mrecip=options. (ix86_function_specific_save): Save recip_mask_explicit. (ix86_function_specific_restore): Restore recip_mask_explicit. * doc/invoke.texi (ix86 Options): Document the new option. From-SVN: r179608
2011-10-05Add support for lzd and popc instructions on sparc.David S. Miller1-1/+10
gcc/ * config/sparc/sparc.opt (POPC): New option. * doc/invoke.texi: Document it. * config/sparc/sparc.c (sparc_option_override): Enable MASK_POPC by default on Niagara-2 and later. * config/sparc/sparc.h (CLZ_DEFINED_VALUE_AT_ZERO): Define. * config/sparc/sparc.md (SIDI): New mode iterator. (ffsdi2): Delete commented out pattern and comments. (popcount<mode>2, clz<mode>2): New expanders. (*popcount<mode>_sp64, popcountsi_v8plus, popcountdi_v8plus, *clzdi_sp64, clzdi_v8plus, *clzsi_sp64, clzsi_v8plus): New insns. gcc/testsuite/ * gcc.target/sparc/lzd.c: New test. * gcc.target/sparc/popc.c: New test. From-SVN: r179591
2011-10-05rx.opt (mpid): Define.DJ Delorie1-7/+39
* config/rx/rx.opt (mpid): Define. * config/rx/t-rx (MULTILIB_OPTIONS): Add -mpid (MULTILIB_DIRNAMES): Add pid. * config/rx/rx.c (rx_gp_base_regnum_val, rx_pid_base_regnum_val) (rx_num_interrupt_regs): New variable. (rx_gp_base_regnum): New function. Returns the number of the small data area register. (rx_pid_base_regnum): New function. Returns the number of the pid base register. (rx_decl_for_addr): New function. Returns the symbolic part of a MEM. (rx_pid_data_operand): New function. Returns whether an object is in the position independent data area. (rx_legitimize_address): New function. Puts undecided PID objects in the PID data area. (rx_is_legitimate_address): Add support for PID operands. (rx_print_operand_address): Likewise. (rx_print_operand): Likewise. (rx_maybe_pidify_operand): New function. Determine if an operand is suitable for PID addressing. (rx_gen_move_template): Add PID support. (rx_conditional_register_usage): Likewise. (rx_option_override): Initialise rx_num_interrupt_regs. (rx_is_legitimate_constant): Add support for PID constants. (TARGET_LEGITIMIZE_ADDRESS): Define. * config/rx/constraints.md (Rpid): Define. (Rpda): Define. * config/rx/rx.md (UNSPEC_PID_ADDR): Define. (tablejump): Add PID support. (mov<>): Likewise. (mov<>_internal): Likewise. (addsi3): Convert to an expander. Add PID support. (pid_addr): New pattern. * config/rx/rx.h (CPP_SPEC): Define. (ASM_SPEC): Pass -mpid and -mint-register on to assembler. (CASE_VECTOR_PC_RELATIVE): Define. (JUMP_TABLES_IN_TEXT_SECTION): Enable for PID mode. * config/rx/rx-protos.h (rx_maybe_pidify_operand): Prototype. * doc/invoke.texi (RX Options): Document -mpid command line option. Co-Authored-By: Nick Clifton <nickc@redhat.com> From-SVN: r179558
2011-10-05invoke.texi (-fshrink-wrap): Document.Bernd Schmidt1-4/+10
* doc/invoke.texi (-fshrink-wrap): Document. * opts.c (default_options_table): Add it. * common.opt (fshrink-wrap): Add. * function.c (emit_return_into_block): Remove useless declaration. (record_hard_reg_uses_1, record_hard_reg_uses, frame_required_for_rtx, requires_stack_frame_p, gen_return_pattern): New static functions. (emit_return_into_block): New arg simple_p. All callers changed. Use gen_return_pattern. (thread_prologue_and_epilogue_insns): Implement shrink-wrapping. * config/i386/i386.md (return): Expand into a simple_return. (simple_return): New expander): (simple_return_internal, simple_return_internal_long, simple_return_pop_internal_long, simple_return_indirect_internal): Renamed from return_internal, return_internal_long, return_pop_internal_long and return_indirect_internal; changed to use simple_return. * config/i386/i386.c (ix86_expand_epilogue): Adjust to expand simple returns. (ix86_pad_returns): Likewise. * function.h (struct rtl_data): Add member shrink_wrapped. * cfgcleanup.c (outgoing_edges_match): If shrink-wrapped, edges that are not jumps or sibcalls can't be compared. * gcc.target/i386/sw-1.c: New test. From-SVN: r179553
2011-10-04Add support for more sparc VIS 3.0 instructions.David S. Miller1-0/+11
gcc/ * config/sparc/sparc.md (UNSPEC_FHADD, UNSPEC_FHSUB, UNSPEC_XMUL): New unspecs. (muldi3_v8plus): Use output_v8plus_mult. (*naddsf3, *nadddf3, *nmulsf3, *nmuldf3, *nmuldf3_extend): New VIS 3.0 combiner patterns. (fhaddsf_vis, fhadddf_vis, fhsubsf_vis, fhsubdf_vis, fnhaddsf_vis, fnhaddf_vis, umulxhi_vis, *umulxhi_sp64, umulxhi_v8plus, xmulx_vis, *xmulx_sp64, xmulx_v8plus, xmulxhi_vis, *xmulxhi_sp64, xmulxhi_v8plus): New VIS 3.0 builtins patterns. * config/sparc/sparc.c (sparc_vis_init_builtins): Emit new builtins. (output_v8plus_mult): New function. * config/sparc/sparc-protos.h: Declare it. * config/sparc/visintrin.h (__vis_fhadds, __vis_fhaddd, __vis_fhsubs, __vis_fhsubd, __vis_fnhadds, __vis_fnhaddd, __vis_umulxhi, __vis_xmulx, __vis_xmulxhi): New intrinsics. * doc/extend.texi: Document new builtins. gcc/testsuite/ * gcc.target/sparc/fhalve.c: New test. * gcc.target/sparc/fnegop.c: New test. * gcc.target/sparc/xmul.c: New test. From-SVN: r179535
2011-10-03Vector shuffling patch from Artem Shinkarov.Artjoms Sinkarovs1-0/+26
From-SVN: r179462
2011-10-02* invoke.texi (SPARC Options): Refer to GNU/Linux.Gerald Pfeifer1-2/+2
From-SVN: r179434
2011-10-01Start adding support for VIS 3.0 instructions.David S. Miller2-3/+55
gcc/ * config/sparc/sparc.opt (VIS3): New option. * doc/invoke.texi: Document it. * config/sparc/sparc.h: Force TARGET_VIS3 to zero if assembler is not capable of such instructions. * config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__ to 0x300 when TARGET_VIS3. * config/sparc/sparc-modes.def: Create 16-byte vector modes. * config/sparc/sparc.md (UNSPEC_CMASK8, UNSPEC_CMASK16, UNSPEC_CMASK32, UNSPEC_FCHKSM16, UNSPEC_PDISTN, UNSPC_FUCMP): New unspecs. (V64N8, VASS): New mode iterators. (vis3_shift, vis3_addsub_ss): New code iterators. (vbits, vconstr): New mode attributes. (vis3_shift_insn, vis3_addsub_ss_insn): New code attributes. (cmask8<P:mode>_vis, cmask16<P:mode>_vis, cmask32<P:mode>_vis, fchksm16_vis, <vis3_shift_insn><vbits>_vis, pdistn<mode>_vis, fmean16_vis, fpadd64_vis, fpsub64_vis, <vis3_addsub_ss_insn><vbits>_vis, fucmp<code>8<P:mode>_vis): New VIS 3.0 instruction patterns. * config/sparc/sparc.c (sparc_option_override): Set MASK_VIS3 by default when targetting capable cpus. TARGET_VIS3 implies TARGET_VIS2 and TARGET_VIS, and clear them when TARGET_FPU is disabled. (sparc_vis_init_builtins): Emit new VIS 3.0 builtins. (sparc_fold_builtin): Do not eliminate cmask{8,16,32} when result is ignored. * config/sparc/visintrin.h (__vis_cmask8, __vis_cmask16, __vis_cmask32, __vis_fchksm16, __vis_fsll16, __vis_fslas16, __vis_fsrl16, __vis_fsra16, __vis_fsll32, __vis_fslas32, __vis_fsrl32, __vis_fsra32, __vis_pdistn, __vis_fmean16, __vis_fpadd64, __vis_fpsub64, __vis_fpadds16, __vis_fpadds16s, __vis_fpsubs16, __vis_fpsubs16s, __vis_fpadds32, __vis_fpadds32s, __vis_fpsubs32, __vis_fpsubs32s, __vis_fucmple8, __vis_fucmpne8, __vis_fucmpgt8, __vis_fucmpeq8): New VIS 3.0 interfaces. * doc/extend.texi: Document new VIS 3.0 builtins. gcc/testsuite/ * gcc.target/sparc/cmask.c: New test. * gcc.target/sparc/fpadds.c: New test. * gcc.target/sparc/fshift.c: New test. * gcc.target/sparc/fucmp.c: New test. * gcc.target/sparc/vis3misc.c: New test. From-SVN: r179421
2011-09-30Add missing ','.H.J. Lu1-2/+2
2011-09-30 H.J. Lu <hongjiu.lu@intel.com> * doc/extend.texi: Add missing ','. From-SVN: r179397
2011-09-30haifa-sched.c (modulo_ii, [...]): New static variables.Bernd Schmidt1-0/+5
* haifa-sched.c (modulo_ii, modulo_max_states, modulo_n_insns, modulo_insns_scheduled, modulo_iter0_max_uid, modulo_backtracks_left, modulo_last_stage): New static variables. (set_modulo_params, discard_delay_pairs_above): New functions. (struct delay_pair): New member stages. (htab_i2_traverse, htab_i1_traverse): New static functions. (record_delay_slot_pair): New arg stages. All callers changed. Record it. (pair_delay): Take stages into account. (add_delay_dependencies): Don't do so for stage pairs. (struct sched_block_state): New member modulo_epilogue. (save_backtrack_point): Don't set SHADOW_P for stage pairs. (unschedule_insns_until): Decrease modulo_insns_scheduled. Set HARD_DEP without using or. (resolve_dependencies): New static function. (prune_ready_list): New arg modulo_epilogue_p. All callers changed. If it is true, allow only insns with INSN_EXACT_TICK set. (schedule_block): Return bool, always true for normal scheduling, true or false depending on modulo scheduling success otherwise. Add bookkeeping for modulo scheduling, and call resolve_dependencies on everything left over after a modulo schedule. (haifa_sched_init): Remove check_cfg call. Clear modulo_ii. * sched-int.h (schedule_block, record_delay_slot_pair): Adjust declarations. (set_modulo_params, discard_delay_pairs_above): Declare. * params.def (PARAM_MAX_MODULO_BACKTRACK_ATTEMPS): New. * doc/invoke.texi (--param): Document it. From-SVN: r179383
2011-09-30Add sparc VIS 2.0 builtins, intrinsics, and option to control them.David S. Miller2-1/+29
gcc/ * config/sparc/sparc.opt (VIS2): New option. * doc/invoke.texi: Document it. * config/sparc/sparc.md (UNSPEC_EDGE8N, UNSPEC_EDGE8LN, UNSPEC_EDGE16N, UNSPEC_EDGE16LN, UNSPEC_EDGE32N, UNSPEC_EDGE32LN, UNSPEC_BSHUFFLE): New unspecs. (define_attr type): New insn type 'edgen'. (bmask<P:mode>_vis, bshuffle<V64I:mode>_vis, edge8n<P:mode>_vis, edge8ln<P:mode>_vis, edge16n<P:mode>_vis, edge16ln<P:mode>_vis, edge32n<P:mode>_vis, edge32ln<P:mode>_vis): New insn VIS 2.0 patterns. * niagara.md: Handle edgen. * niagara2.md: Likewise. * ultra1_2.md: Likewise. * ultra3.md: Likewise. * config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__ to 0x200 when TARGET_VIS2. * config/sparc/sparc.c (sparc_option_override): Set MASK_VIS2 by default when targetting capable cpus. TARGET_VIS2 implies TARGET_VIS, clear and it when TARGET_FPU is disabled. (sparc_vis_init_builtins): Emit new VIS 2.0 builtins. (sparc_expand_builtin): Fix predicate indexing when builtin returns void. (sparc_fold_builtin): Do not eliminate bmask when result is ignored. * config/sparc/visintrin.h (__vis_bmask, __vis_bshuffledi, __vis_bshufflev2si, __vis_bshufflev4hi, __vis_bshufflev8qi, __vis_edge8n, __vis_edge8ln, __vis_edge16n, __vis_edge16ln, __vis_edge32n, __vis_edge32ln): New VIS 2.0 interfaces. * doc/extend.texi: Document new VIS 2.0 builtins. gcc/testsuite/ * gcc.target/sparc/bmaskbshuf.c: New test. * gcc.target/sparc/edgen.c: New test. From-SVN: r179376
2011-09-29expr.c (do_store_flag): Expand vector comparison by building an appropriate ↵Artjoms Sinkarovs1-0/+23
VEC_COND_EXPR. 2011-09-29 Artjoms Sinkarovs <artyom.shinkaroff@gmail.com> * expr.c (do_store_flag): Expand vector comparison by building an appropriate VEC_COND_EXPR. * c-typeck.c (build_binary_op): Typecheck vector comparisons. (c_objc_common_truthvalue_conversion): Adjust. * tree-vect-generic.c (do_compare): Helper function. (expand_vector_comparison): Check if hardware supports vector comparison of the given type or expand vector piecewise. (expand_vector_operation): Treat comparison as binary operation of vector type. (expand_vector_operations_1): Adjust. * gcc.c-torture/execute/vector-compare-1.c: New testcase. * gcc.c-torture/execute/vector-compare-2.c: Likewise. * gcc.dg/vector-compare-1.c: Likewise. * gcc.dg/vector-compare-2.c: Likewise. From-SVN: r179342
2011-09-29Add sparc 3D array addressing VIS intrinsics.David S. Miller1-0/+4
gcc/ * config/sparc/sparc.md (UNSPEC_ARRAY8, UNSPEC_ARRAY16, UNSPEC_ARRAY32): New unspec. (define_attr type): New type 'array'. (array{8,16,32}<P:mode>_vis): New patterns. * config/sparc/ultra1_2.md: Add reservations for 'array'. * config/sparc/ultra3.md: Likewise. * config/sparc/niagara.md: Likewise. * config/sparc/niagara2.md: Likewise. * config/sparc/sparc.c (sparc_vis_init_builtins): Build new array builtins. * config/sparc/visintrin.h (__vis_array8, __vis_array16, __vis_array32): New. * doc/extend.texi: Document new VIS builtins. gcc/testsuite/ * gcc.target/sparc/array.c: New test. From-SVN: r179334
2011-09-27re PR middle-end/43864 (Same basic blocks should be merged)Tom de Vries1-2/+17
2011-09-27 Tom de Vries <tom@codesourcery.com> PR middle-end/43864 * tree-ssa-tail-merge.c: New file. (struct same_succ_def): Define. (same_succ, const_same_succ): New typedef. (struct bb_cluster_def): Define. (bb_cluster, const_bb_cluster): New typedef. (struct aux_bb_info): Define. (BB_SIZE, BB_SAME_SUCC, BB_CLUSTER, BB_VOP_AT_EXIT): Define. (gvn_uses_equal): New function. (same_succ_print, same_succ_print_traverse, update_dep_bb) (stmt_update_dep_bb, local_def, same_succ_hash) (inverse_flags, same_succ_equal, same_succ_alloc, same_succ_delete) (same_succ_reset): New function. (same_succ_htab, same_succ_edge_flags) (deleted_bbs, deleted_bb_preds): New var. (debug_same_succ): New function. (worklist): New var. (print_worklist, add_to_worklist, find_same_succ_bb, find_same_succ) (init_worklist, delete_worklist, delete_basic_block_same_succ) (same_succ_flush_bbs, purge_bbs, update_worklist): New function. (print_cluster, debug_cluster, update_rep_bb) (add_bb_to_cluster, new_cluster, delete_cluster): New function. (all_clusters): New var. (alloc_cluster_vectors, reset_cluster_vectors, delete_cluster_vectors) (merge_clusters, set_cluster): New function. (gimple_equal_p, gsi_advance_bw_nondebug_nonlocal, find_duplicate) (same_phi_alternatives_1, same_phi_alternatives, bb_has_non_vop_phi) (deps_ok_for_redirect_from_bb_to_bb, deps_ok_for_redirect) (find_clusters_1, find_clusters): New function. (update_vuses, vop_phi, vop_at_entry, replace_block_by): New function. (update_bbs): New var. (apply_clusters): New function. (update_debug_stmt, update_debug_stmts): New function. (tail_merge_optimize): New function. tree-pass.h (tail_merge_optimize): Declare. * tree-ssa-pre.c (execute_pre): Use tail_merge_optimize. * Makefile.in (OBJS-common): Add tree-ssa-tail-merge.o. (tree-ssa-tail-merge.o): New rule. * opts.c (default_options_table): Set OPT_ftree_tail_merge by default at OPT_LEVELS_2_PLUS. * tree-ssa-sccvn.c (vn_valueize): Move to ... * tree-ssa-sccvn.h (vn_valueize): Here. * timevar.def (TV_TREE_TAIL_MERGE): New timevar. * common.opt (ftree-tail-merge): New switch. * params.def (PARAM_MAX_TAIL_MERGE_COMPARISONS) (PARAM_MAX_TAIL_MERGE_ITERATIONS): New parameter. * doc/invoke.texi (Optimization Options, -O2): Add -ftree-tail-merge. (-ftree-tail-merge, max-tail-merge-comparisons) (max-tail-merge-iterations): New item. From-SVN: r179275
2011-09-27invoke.texi (ffat-lto-objects): Document.Andi Kleen1-2/+18
* doc/invoke.texi (ffat-lto-objects): Document. * toplev.c (compile_file): Do not output assembly when doing slim lto; Output __gnu_slim_lto when doing slim lto. * cgraphunit.c (ipa_passes): Do only analysis when producing slim lto. (cgraph_optimize): Return early when doing slim lto. * opts.c (finish_options): Complain about lack of linker plugin when doing slim lto. * common.opt (ffat-lto-objects): New. Co-Authored-By: Jan Hubicka <jh@suse.cz> From-SVN: r179271
2011-09-26Add explicit VIS intrinsics for addition and subtraction.David S. Miller1-0/+10
gcc/ * config/sparc/sparc.c (sparc_vis_init_builtins): Add explicit builtins for VIS vector addition and subtraction. * config/sparc/visintrin.h (__vis_fpadd16, __vis_fpadd16s, __vis_fpadd32, __vis_fpadd32s, __vis_fpsub16, __vis_fpsub16s, __vis_fpsub32, __vis_fpsub32s): New. * doc/extend.texi: Document new VIS intrinsics. gcc/testsuite/ * gcc.target/sparc/fpaddsubi.c: New test. From-SVN: r179235
2011-09-26Improve code generation for edge and pixel-compare...David S. Miller1-15/+15
Improve code generation for edge and pixel-compare, specifically avoid sign and zero extensions on 64-bit and allow such instructions to be placed in delay slots. gcc/ * config/sparc/sparc.md (edge{8,16,32}{,l}): Return Pmode. (fcmp{le,ne,gt,eq}{16,32}): Likewise. * config/sparc/visintrin.h: Update edge and pixel-compare intrinsics to return 'long' instead of 'int'. * doc/extend.texi: Update documentation to match. * config/sparc/sparc.c (eligible_for_return_delay): When leaf or flat, allow any instruction. Otherwise, when V9 allow parallels which consist only of sets to registers outside of %o0 to %o5. (sparc_vis_init_builtins): Update VIS builtin types for edge and pixel-compare. gcc/testsuite/ * gcc.target/sparc/edge.c: Update for new return types. * gcc.target/sparc/fcmp.c: Likewise. From-SVN: r179227
2011-09-26tm.texi: Correct documentation for TARGET_ADDR_SPACE_SUBSET_P.Bingfeng Mei1-1/+1
2011-09-26 Bingfeng Mei <bmei@broadcom.com> * doc/tm.texi: Correct documentation for TARGET_ADDR_SPACE_SUBSET_P. * target.def: (addr_space_subset_p): Likewise. From-SVN: r179195
2011-09-25Add support for floating-point fused multiply-add on Sparc.David S. Miller1-1/+11
* configure.ac: Add feature check to make sure the assembler supports the FMAF, HPC, and VIS 3.0 instructions found on Niagara-3 and later cpus. * configure: Rebuild. * config.in: Likewise. * config/sparc/sparc.opt: New option '-mfmaf'. * config/sparc/sparc.md: Add float fused multiply-add patterns. * config/sparc/sparc.h (AS_NIAGARA3_FLAG): New macro. (ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Use it, as needed. * config/sparc/sol2.h (ASM_CPU32_DEFAULT_SPEC, ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Likewise. * config/sparc/sparc.c (sparc_option_override): Turn MASK_FMAF on by default for Niagara-3 and later. Turn it off if TARGET_FPU is disabled. (sparc_rtx_costs): Handle 'FMA'. * doc/invoke.texi: Document -mfmaf. From-SVN: r179174
2011-09-24Teach sparc backend about %gsr register and add intrinsics to access it.David S. Miller1-0/+3
* config/sparc/sparc.h (FIRST_PSEUDO_REGISTER): Bump to 103. (SPARC_GSR_REG): Define. (FIXED_REGISTERS): Mark GSR as fixed. (CALL_USED_REGISTERS): Mark GSR as call used. (HARD_REGNO_NREGS): GSR is always 1 register. (REG_CLASS_CONTENTS): Add GSR to ALL_REGS. (REG_ALLOC_ORDER, REG_LEAF_ALLOC_ORDER): Add GSR to the end. (REGISTER_NAMES): Add "%gsr". * config/sparc/sparc.md (UNSPEC_ALIGNADDR, UNSPEC_ALIGNADDRL): Delete. (UNSPEC_WRGSR): New unspec. (GSR_REG): New constant. (type): Add new insn type 'gsr'. (fpack16_vis, fpackfix_vis, fpack32_vis, faligndata<V64I:MODE>_vis)): Add use of GSR_REG. (wrgsr_vis, *wrgsr_sp64, wrgsr_v8plus, rdgsr_vis, *rdgsr_sp64, rdgsr_v8plus): New expanders and insns. (alignaddr<P:mode>_vis, alignaddrl<P:mode>_vis): Reimplement using patterns which show that this is a plus in addition to a modification of GSR_REG, instead of an unspec. * config/sparc/ultra1_2.md: Handle 'gsr'. * config/sparc/ultra3.md: Likewise. * config/sparc/niagara.md: Likewise. * config/sparc/niagara2.md: Likewise. * config/sparc/sparc.c (leaf_reg_remap, sparc_leaf_regs): Fill out end of table. (sparc_option_override): Make -mvis imply -mv8plus. (hard_32bit_mode_classes, hard_64bit_mode_classes): Add entries for %gsr. (sparc_vis_init_builtins): Build __builtin_vis_write_gsr and __builtin_vis_read_gsr. (sparc_expand_buildin): Handle builtins that take one argument and return void. (sparc_fold_builtin): Never fold writes to %gsr. * config/sparc/visintrin.h (__vis_write_gsr, __vis_read_gsr): New. * doc/extend.texi: Document new VIS intrinsics. From-SVN: r179159
2011-09-21Add pixel compare VIS intrinsics.David S. Miller1-0/+9
* config/sparc/sparc.md (UNSPEC_FCMPLE, UNSPEC_FCMPNE, UNSPEC_FCMPGT, UNSPEC_FCMPEQ): New unspec codes. (fcmple16_vis, fcmple32_vis, fcmpne16_vis, fcmpne32_vis, fcmpgt16_vis, fcmpgt32_vis, fcmpeq16_vis, fcmpeq32_vis): New patterns. * config/sparc/sparc.c (sparc_vis_init_builtins): Create builtins for new pixel compare VIS patterns. * config/sparc/visintrin.h (__vis_fcmple16, __vis_fcmple32, __vis_fcmpne16, __vis_fcmpne32, __vis_fcmpgt16, __vis_fcmpgt32, __vis_fcmpeq16, __vis_fcmpeq32): New. * doc/extend.texi: Document new pixel compare VIS intrinsics. From-SVN: r179072
2011-09-20sparc.md (UNSPEC_ALIGNADDRL): New unspec.David S. Miller1-11/+12
* config/sparc/sparc.md (UNSPEC_ALIGNADDRL): New unspec. (aligneddrl<P:mode>_vis): New pattern. (edge8_vis, edge8l_vis, edge16_vis, edge16l_vis, edge32_vis, edge32l_vis): Adjust to take Pmode arguments, and return SImode. * config/sparc/sparc.c (sparc_vis_init_builtins): Handle new alignaddrl insn, and adjust edge operations for updated types. * config/sparc/visintrin.h: Likewise. * doc/extend.texi: Make typing in VIS documentation match reality. From-SVN: r179012
2011-09-17sparc.md (UNSPEC_EDGE8, [...]): New unspecs.David S. Miller1-0/+7
* config/sparc/sparc.md (UNSPEC_EDGE8, UNSPEC_EDGE8L, UNSPEC_EDGE16, UNSPEC_EDGE16L, UNSPEC_EDGE32, UNSPEC_EDGE32L): New unspecs. (define_attr type): New type 'edge'. (edge8_vis, edge8l_vis, edge16_vis, edge16l_vis, edge32_vis, edge32l_vis): New patterns. * config/sparc/ultra1_2.md: Add insn reservation for 'edge'. * config/sparc/ultra3.md: Likewise. * config/sparc/niagara.md: Likewise. * config/sparc/niagara2.md: Likewise. * config/sparc/sparc.d (sparc_vis_init_builtins): Generate builtins for VIS edge instructions. * config/sparc/visintrin.h (__vis_edge8, __vis_edge8l) (__vis_edge16, __vis_edge16l, __vis_edge32, __vis_edge32l): New intrinsics. (__v8qi, __v4qi): Make unsigned. (__vis_faligndatadi, ___vis_faligndatav2si, __vis_faligndatav4hi, __vis_faligndatav8qi, __vis_fmul8x16au, __vis_fmul8x16al, __vis_fpack32): Fix types. * doc/extend.texi: Document new 'edge' VIS intrinsics. From-SVN: r178931
2011-09-09arm-cores.def (generic-armv7-a): New architecture.Andrew Stubbs1-0/+11
2011-09-09 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/arm/arm-cores.def (generic-armv7-a): New architecture. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/arm.c (arm_file_start): Output .arch directive when user passes -mcpu=generic-*. (arm_issue_rate): Add genericv7a support. * config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec. (ASM_CPU_SPEC): New define. * config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec). * config/arm/semi.h (ASM_SPEC): Likewise. * doc/invoke.texi (ARM Options): Document -mcpu=generic-* and -mtune=generic-*. From-SVN: r178731
2011-09-08PR c++/33255 - Support -Wunused-local-typedefs warningDodji Seketeli1-2/+7
gcc/ * c-decl.c (lookup_name): Use the new maybe_record_typedef_use. (pushdecl): Use the new record_locally_defined_typedef. (store_parm_decls): Allocate cfun->language. (finish_function): Use the new maybe_warn_unused_local_typedefs, and free cfun->language. (c_push_function_context): Allocate cfun->language here only if needed. (c_pop_function_context): Likewise, mark cfun->language for collection only when it should be done. * c-common.c (handle_used_attribute): Don't ignore TYPE_DECL nodes. * c-typeck.c (c_expr_sizeof_type, c_cast_expr): Use the new maybe_record_local_typedef_use. gcc/c-family * c-common.h (struct c_language_function::local_typedefs): New field. (record_locally_defined_typedef, maybe_record_typedef_use) (maybe_warn_unused_local_typedefs): Declare new functions. * c-common.c (record_locally_defined_typedef) (maybe_record_typedef_use) (maybe_warn_unused_local_typedefs): Define new functions. * c.opt: Declare new -Wunused-local-typedefs flag. gcc/cp * name-lookup.c (pushdecl_maybe_friend_1): Use the new record_locally_defined_typedef. * decl.c (finish_function): Use the new maybe_warn_unused_local_typedefs. (grokfield): Use the new record_locally_defined_typedef. * parser.c (lookup_name): Use the new maybe_record_typedef_use. gcc/doc/ * invoke.texi: Update documentation for -Wunused-local-typedefs. gcc/testsuite/ * g++.dg/warn/Wunused-local-typedefs.C: New test file. * c-c++-common/Wunused-local-typedefs.c: Likewise. libstdc++-v3/ * include/ext/bitmap_allocator.h (__detail::__mini_vector::__lower_bound): Remove unused typedef. * src/istream.cc (std::operator>>(basic_istream<char>& __in, basic_string<char>& __str)): Likewise. (std::getline): Likewise. * src/valarray.cc (__valarray_product): Likewise. From-SVN: r178692
2011-09-06Update documentation about tm_p.hMichael Meissner1-2/+10
From-SVN: r178618
2011-09-06PR middle-end/44382: Tree reassociation improvementEnkovich Ilya3-0/+12
gcc/ 2011-09-06 Enkovich Ilya <ilya.enkovich@intel.com> PR middle-end/44382 * target.def (reassociation_width): New hook. * doc/tm.texi.in (reassociation_width): Likewise. * doc/tm.texi (reassociation_width): Likewise. * doc/invoke.texi (tree-reassoc-width): New param documented. * hooks.h (hook_int_uint_mode_1): New default hook. * hooks.c (hook_int_uint_mode_1): Likewise. * config/i386/i386.h (ix86_tune_indices): Add X86_TUNE_REASSOC_INT_TO_PARALLEL and X86_TUNE_REASSOC_FP_TO_PARALLEL. (TARGET_REASSOC_INT_TO_PARALLEL): New. (TARGET_REASSOC_FP_TO_PARALLEL): Likewise. * config/i386/i386.c (initial_ix86_tune_features): Add X86_TUNE_REASSOC_INT_TO_PARALLEL and X86_TUNE_REASSOC_FP_TO_PARALLEL. (ix86_reassociation_width) implementation of new hook for i386 target. * params.def (PARAM_TREE_REASSOC_WIDTH): New param added. * tree-ssa-reassoc.c (get_required_cycles): New function. (get_reassociation_width): Likewise. (swap_ops_for_binary_stmt): Likewise. (rewrite_expr_tree_parallel): Likewise. (rewrite_expr_tree): Refactored. Part of code moved into swap_ops_for_binary_stmt. (reassociate_bb): Now checks reassociation width to be used and call rewrite_expr_tree_parallel instead of rewrite_expr_tree if needed. gcc/testsuite/ 2011-09-06 Enkovich Ilya <ilya.enkovich@intel.com> * gcc.dg/tree-ssa/pr38533.c (dg-options): Added option --param tree-reassoc-width=1. * gcc.dg/tree-ssa/reassoc-24.c: New test. * gcc.dg/tree-ssa/reassoc-25.c: Likewise. From-SVN: r178602
2011-09-05sparc-opts.h (PROCESSOR_NIAGARA3, [...]): New.David S. Miller1-5/+9
* config/sparc/sparc-opts.h (PROCESSOR_NIAGARA3, PROCESSOR_NIAGARA4): New. * config/sparc/sparc.opt: Handle new processor types. * config/sparc/sparc.md: Add to "cpu" attribute. * config/sparc/sparc.h (TARGET_CPU_niagara3, TARGET_CPU_niagara4): New, treat as niagara2. * config/sparc/linux64.h: Handle niagara3 and niagara4 like niagara2. * config/sparc/sol2.h: Likewise. * config/sparc/niagara2.md: Schedule niagara3 like niagara2. * config/sparc/sparc.c (sparc_option_override): Add niagara3 and niagara4 handling. (sparc32_initialize_trampoline): Likewise. (sparc64_initialize_trampoline): Likewise. (sparc_use_sched_lookahead): Likewise. (sparc_issue_rate): Likewise. (sparc_register_move_cost): Likewise. * config/sparc/driver-sparc.c (cpu_names): Use niagara3 and niagara4 as appropriate. * doc/invoke.texi: Document new processor types. From-SVN: r178554
2011-09-05config.host: Add driver-sparc.o and sparc/x-sparc on native sparc*-*-linux* ↵David S. Miller1-3/+3
builds. * config.host: Add driver-sparc.o and sparc/x-sparc on native sparc*-*-linux* builds. * config/sparc/driver-sparc.c: Correct Linux strings. * config/sparc/linux.h: Add DRIVER_SELF_SPECS. * config/sparc/linux64.h: Likewise. * doc/invoke.texi: Document that Linux also supports -mcpu=native and -mtune=native on sparc. From-SVN: r178553
2011-09-02re PR tree-optimization/27460 (Does not vectorize statements with mixed type ↵Richard Guenther1-0/+11
COND_EXPRs) 2011-09-02 Richard Guenther <rguenther@suse.de> PR tree-optimization/27460 PR middle-end/29269 * doc/md.texi (vcond): Document. * genopinit.c (optabs): Turn vcond{,u}_optab into a conversion optab with two modes. * optabs.h (enum convert_optab_index): Add COI_vcond, COI_vcondu. (enum direct_optab_index): Remove DOI_vcond, DOI_vcondu. (vcond_optab): Adjust. (vcondu_optab): Likewise. (expand_vec_cond_expr_p): Adjust prototype. * optabs.c (get_vcond_icode): Adjust. (expand_vec_cond_expr_p): Likewise. (expand_vec_cond_expr): Likewise. * tree-vect-stmts.c (vect_is_simple_cond): Return the comparison vector type. (vectorizable_condition): Allow differing types for comparison and result. * config/i386/i386.c (ix86_expand_sse_cmp): Use proper mode for the comparison. * config/i386/sse.md (vcond<mode>): Split to vcond<V_256:mode><VF_256:mode>, vcond<V_128:mode><VF_128:mode>, vcond<V_128:mode><VI124_128:mode> and vcondu<V_128:mode><VI124_128:mode>. (vcondv2di): Change to vcond<VI8F_128:mode>v2di. (vconduv2di): Likewise. * config/arm/neon.md (vcond<mode>): Change to vcond*<mode><mode>. (vcondu<mode>): Likewise. * config/ia64/vect.md (vcond<mode>): Likewise. (vcondu<mode>): Likewise. (vcondv2sf): Likewise. * config/mips/mips-ps-3d.md (vcondv2sf): Likewise. * config/rs6000/paired.md (vcondv2sf): Likewise. * config/rs6000/vector.md (vcond<mode>): Likewise. (vcondu<mode>): Likewise. * config/spu/spu.md (vcond<mode>): Likewise. (vcondu<mode>): Likewise. * gcc.dg/vect/vect-cond-7.c: New testcase. From-SVN: r178480
2011-08-31md.texi: Describe the use of match_tests in attribute tests.Richard Sandiford1-0/+24
gcc/ * doc/md.texi: Describe the use of match_tests in attribute tests. * rtl.def (MATCH_TEST): Update commentary. * genattrtab.c (attr_copy_rtx, check_attr_test, clear_struct_flag) (write_test_expr, walk_attr_value): Handle MATCH_TEST. From-SVN: r178388
2011-08-31generic.texi (Types for C++): CP_TYPE_QUALS -> cp_type_quals.Marc Glisse1-3/+3
2011-08-31 Marc Glisse <marc.glisse@inria.fr> * doc/generic.texi (Types for C++): CP_TYPE_QUALS -> cp_type_quals. From-SVN: r178369
2011-08-30genautomata.c (NO_COMB_OPTION): New macro.Bernd Schmidt1-0/+7
* genautomata.c (NO_COMB_OPTION): New macro. (no_comb_flag): New static variable. (gen_automata_option): Handle NO_COMB_OPTION. (comb_vect_p): False if no_comb_flag. (add_vect): Move computation of min/max values. Return early if no_comb_flag. * doc/md.texi (automata_option): Document no-comb-vect. From-SVN: r178295
2011-08-29Change default for -msave-toc-indirectMichael Meissner1-1/+11
From-SVN: r178260
2011-08-27rtl.texi (simple_return): Document.Bernd Schmidt2-9/+32
* doc/rtl.texi (simple_return): Document. (parallel, PATTERN): Here too. * doc/md.texi (return): Mention it's allowed to expand to simple_return in some cases. (simple_return): Document standard pattern. * gengenrtl.c (special_rtx): SIMPLE_RETURN is special. * final.c (final_scan_insn): Use ANY_RETURN_P on body. * reorg.c (function_return_label, function_simple_return_label): New static variables, replacing... (end_of_function_label): ... this. (simplejump_or_return_p): New static function. (optimize_skip, steal_delay_list_from_fallthrough, fill_slots_from_thread): Use it. (relax_delay_slots): Likewise. Use ANY_RETURN_P on body. (rare_destination, follow_jumps): Use ANY_RETURN_P on body. (find_end_label): Take a new arg which is one of the two return rtxs. Depending on which, set either function_return_label or function_simple_return_label. All callers changed. (make_return_insns): Make both kinds. (dbr_schedule): Adjust for two kinds of end labels. * function.c (emit_return_into_block): Set JUMP_LABEL properly. * genemit.c (gen_exp): Handle SIMPLE_RETURN. (gen_expand, gen_split): Use ANY_RETURN_P. * df-scan.c (df_uses_record): Handle SIMPLE_RETURN. * rtl.def (SIMPLE_RETURN): New code. * ifcvt.c (find_if_case_1): Be more careful about redirecting jumps to the EXIT_BLOCK. * jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p, returnjump_p_1): Handle SIMPLE_RETURNs. * print-rtl.c (print_rtx): Likewise. * rtl.c (copy_rtx): Likewise. * bt-load.c (compute_defs_uses_and_gen): Use ANY_RETURN_P. * combine.c (simplify_set): Likewise. * resource.c (find_dead_or_set_registers, mark_set_resources): Likewise. * emit-rtl.c (verify_rtx_sharing, classify_insn, copy_insn_1, copy_rtx_if_shared_1, mark_used_flags): Handle SIMPLE_RETURNs. (init_emit_regs): Initialize simple_return_rtx. * cfglayout.c (fixup_reorder_chain): Pass a JUMP_LABEL to force_nonfallthru_and_redirect. * rtl.h (ANY_RETURN_P): Allow SIMPLE_RETURN. (GR_SIMPLE_RETURN): New enum value. (simple_return_rtx): New macro. * basic-block.h (force_nonfallthru_and_redirect): Adjust declaration. * cfgrtl.c (force_nonfallthru_and_redirect): Take a new jump_label argument. All callers changed. Be careful about what kinds of returnjumps to generate. * config/i386/3i86.c (ix86_pad_returns, ix86_count_insn_bb, ix86_pad_short_function): Likewise. * config/arm/arm.c (arm_final_prescan_insn): Handle both kinds of return. * config/mips/mips.md (any_return): New code_iterator. (optab): Add cases for return and simple_return. (return): Expand to a simple_return. (simple_return): New pattern. (*<optab>, *<optab>_internal for any_return): New patterns. (return_internal): Remove. * config/mips/mips.c (mips_expand_epilogue): Make the last insn a simple_return_internal. From-SVN: r178135
2011-08-25md.texi (automata_option): Document collapse-ndfa.Bernd Schmidt1-0/+10
* doc/md.texi (automata_option): Document collapse-ndfa. * genautomata.c (COLLAPSE_OPTION): New macro. (collapse_flag): New static variable. (struct description): New member normal_decls_num. (struct automaton): New members advance_ainsn and collapse_ainsn. (gen_automata_option): Check for COLLAPSE_OPTION. (collapse_ndfa_insn_decl): New static variable. (add_collapse_ndfa_insn_decl, special_decl_p): New functions. (find_arc): If insn is the collapse-ndfa insn, accept any arc we find. (transform_insn_regexps): Call add_collapse_ndfa_insn_decl if necessary. Use normal_decls_num rather than decls_num, remove test for special decls. (create_alt_states, form_ainsn_with_same_reservs): Use special_decl_p. (make_automaton); Likewise. Use the new advance_cycle_insn member of struct automaton. (create_composed_state): Disallow advance-cycle arcs if collapse_flag is set. (NDFA_to_DFA): Don't create composed states for the collapse-ndfa transition. Create the necessary transitions for it. (create_ainsns): Return void. Take an automaton_t argument, and update its ainsn_list, advance_ainsn and collapse_ainsn members. All callers changed. (COLLAPSE_NDFA_VALUE_NAME): New macro. (output_tables): Output code to define it. (output_internal_insn_code_evaluation): Output code to accept const0_rtx as collapse-ndfa transition. (output_default_latencies, output_print_reservation_func, output_print_description): Reorganize loops to use normal_decls_num as loop bound; remove special case for advance_cycle_insn_decl. (initiate_automaton_gen): Handle COLLAPSE_OPTION. (check_automata_insn_issues): Check for collapse_ainsn. (expand_automate): Allocate sufficient space. Initialize normal_decls_num. From-SVN: r178059
2011-08-23re PR middle-end/38509 (Bogus "attempt to free a non-heap object" warning)Mark Heffernan1-1/+8
2011-08-23 Mark Heffernan <meheff@google.com> PR middle-end/38509 * common.opt (Wfree-nonheap-object): New option. * doc/invoke.texi (Warning options): Document -Wfree-nonheap-object. * builtins.c (maybe_emit_free_warning): Add OPT_Wfree_nonheap_object to warning. (expand_builtin): Make warning conditional. From-SVN: r178004
2011-08-23Add BMI2 support.H.J. Lu2-3/+17
gcc/ 2011-08-23 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (type): Add imulx, ishiftx and rotatex. (length_immediate): Handle imulx, ishiftx and rotatex. (imm_disp): Ditto. (isa): Add bmi2. (enabled): Handle bmi2. (w): New mode attribute. (*mul<mode><dwi>3): Split from *<u>mul<mode><dwi>3. (*umul<mode><dwi>3): Ditto. Add imulx BMI2 alternative. (*bmi2_umulditi3_1): New insn pattern. (*bmi2_umulsidi3_1): Ditto. (*umul<mode><dwi>3 splitter): New splitter to avoid flags dependency. (*bmi2_ashl<mode>3_1): New insn pattern. (*ashl<mode>3_1): Add ishiftx BMI2 alternative. (*ashl<mode>3_1 splitter): New splitter to avoid flags dependency. (*bmi2_ashlsi3_1_zext): New insn pattern. (*ashlsi3_1_zext): Add ishiftx BMI2 alternative. (*ashlsi3_1_zext splitter): New splitter to avoid flags dependency. (*bmi2_<shiftrt_insn><mode>3_1): New insn pattern. (*<shiftrt_insn><mode>3_1): Add ishiftx BMI2 alternative. (*<shiftrt_insn><mode>3_1 splitter): New splitter to avoid flags dependency. (*bmi2_<shiftrt_insn>si3_1_zext): New insn pattern. (*<shiftrt_insn>si3_1_zext): Add ishiftx BMI2 alternative. (*<shiftrt_insn>si3_1_zext splitter): New splitter to avoid flags dependency. (*bmi2_rorx<mode>3_1): New insn pattern. (*<rotate_insn><mode>3_1): Add rotatex BMI2 alternative. (*rotate<mode>3_1 splitter): New splitter to avoid flags dependency. (*rotatert<mode>3_1 splitter): Ditto. (*bmi2_rorxsi3_1_zext): New insn pattern. (*<rotate_insn>si3_1_zext): Add rotatex BMI2 alternative. (*rotatesi3_1_zext splitter): New splitter to avoid flags dependency. (*rotatertsi3_1_zext splitter): Ditto. 2011-08-23 Kirill Yukhin <kirill.yukhin@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_BMI2_SET): New. (OPTION_MASK_ISA_BMI2_UNSET): Likewise. (ix86_handle_option): Handle OPT_mbmi2 case. * config.gcc (i[34567]86-*-*): Add bmi2intrin.h. (x86_64-*-*): Likewise. * config/i386/bmi2intrin.h: New file. * config/i386/cpuid.h (bit_BMI2): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect BMI2 feature. * config/i386/i386-c.c (ix86_target_macros_internal): Conditionally define __BMI2__. * config/i386/i386.c (ix86_option_override_internal): Define PTA_BMI2. Handle BMI2 option. (ix86_valid_target_attribute_inner_p): Handle BMI2 option. (print_reg): New code. (ix86_print_operand): Likewise. (ix86_builtins): Add IX86_BUILTIN_BZHI32, IX86_BUILTIN_BZHI64, IX86_BUILTIN_PDEP32, IX86_BUILTIN_PDEP64, IX86_BUILTIN_PEXT32, IX86_BUILTIN_PEXT64. (bdesc_args): Add IX86_BUILTIN_BZHI32, IX86_BUILTIN_BZHI64, IX86_BUILTIN_PDEP32, IX86_BUILTIN_PDEP64, IX86_BUILTIN_PEXT32, IX86_BUILTIN_PEXT64. * config/i386/i386.h (TARGET_BMI2): New. * config/i386/i386.md (UNSPEC_PDEP): New. (UNSPEC_PEXT): Likewise. (*bmi2_bzhi_<mode>3): Likewise. (*bmi2_pdep_<mode>3): Likewise. (*bmi2_pext_<mode>3): Likewise. * config/i386/i386.opt (mbmi2): New. * config/i386/x86intrin.h: Include bmi2intrin.h when __BMI2__ is defined. * doc/extend.texi: Document BMI2 built-in functions. * doc/invoke.texi: Document -mbmi2. gcc/testsuite/ 2011-08-23 Kirill Yukhin <kirill.yukhin@intel.com> * g++.dg/other/i386-2.C: Add -mbmi2 check. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/bmi2-bzhi32-1.c: New testcase. * gcc.target/i386/bmi2-bzhi32-1a.c: Likewise. * gcc.target/i386/bmi2-bzhi64-1.c: Likewise. * gcc.target/i386/bmi2-bzhi64-1a.c: Likewise. * gcc.target/i386/bmi2-mulx32-1.c: Likewise. * gcc.target/i386/bmi2-mulx32-1a.c: Likewise. * gcc.target/i386/bmi2-mulx64-1.c: Likewise. * gcc.target/i386/bmi2-mulx64-1a.c: Likewise. * gcc.target/i386/bmi2-pdep32-1.c: Likewise. * gcc.target/i386/bmi2-pdep32-1a.c: Likewise. * gcc.target/i386/bmi2-pdep64-1.c: Likewise. * gcc.target/i386/bmi2-pdep64-1a.c: Likewise. * gcc.target/i386/bmi2-pext32-1.c: Likewise. * gcc.target/i386/bmi2-pext32-1a.c: Likewise. * gcc.target/i386/bmi2-pext64-1.c: Likewise. * gcc.target/i386/bmi2-pext64-1a.c: Likewise. * gcc.target/i386/bmi2-rorx32-1.c: Likewise. * gcc.target/i386/bmi2-rorx32-1a.c: Likewise. * gcc.target/i386/bmi2-rorx64-1.c: Likewise. * gcc.target/i386/bmi2-rorx64-1a.c: Likewise. * gcc.target/i386/bmi2-sarx32-1.c: Likewise. * gcc.target/i386/bmi2-sarx32-1a.c: Likewise. * gcc.target/i386/bmi2-sarx64-1.c: Likewise. * gcc.target/i386/bmi2-sarx64-1a.c: Likewise. * gcc.target/i386/bmi2-shlx32-1.c: Likewise. * gcc.target/i386/bmi2-shlx32-1a.c: Likewise. * gcc.target/i386/bmi2-shlx64-1.c: Likewise. * gcc.target/i386/bmi2-shlx64-1a.c: Likewise. * gcc.target/i386/bmi2-shrx32-1.c: Likewise. * gcc.target/i386/bmi2-shrx32-1a.c: Likewise. * gcc.target/i386/bmi2-shrx64-1.c: Likewise. * gcc.target/i386/bmi2-shrx64-1a.c: Likewise. * gcc.target/i386/i386.exp (check_effective_target_bmi2): New. * gcc.target/i386/sse-12.c: Add BMI2. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. From-SVN: r178001
2011-08-23re PR middle-end/50161 (wrong code with -fno-tree-ter and __builtin_popcountl)Jakub Jelinek1-10/+10
PR middle-end/50161 * simplify-rtx.c (simplify_const_unary_operation): If op is CONST_INT, don't look at op_mode, but use instead mode. * optabs.c (add_equal_note): For FFS, CLZ, CTZ, CLRSB, POPCOUNT, PARITY and BSWAP use operand mode for operation and TRUNCATE/ZERO_EXTEND if needed. * doc/rtl.texi (ffs, clrsb, clz, ctz, popcount, parity, bswap): Document that operand mode must be same as operation mode, or VOIDmode. * config/avr/avr.md (paritysi2, *parityqihi2.libgcc, *paritysihi2.libgcc, popcountsi2, *popcountsi2.libgcc, *popcountqihi2.libgcc, clzsi2, *clzsihi2.libgcc, ctzsi2, *ctzsihi2.libgcc, ffssi2, *ffssihi2.libgcc): For unary ops use the mode of operand for the operation and add truncate or zero_extend around if needed. * config/c6x/c6x.md (ctzdi2): Likewise. * config/bfin/bfin.md (clrsbsi2, signbitssi2): Likewise. * gcc.dg/pr50161.c: New test. From-SVN: r177991
2011-08-22Add support for AVX2 builtin functions.Kirill Yukhin1-0/+178
2011-08-22 Kirill Yukhin <kirill.yukhin@intel.com> * config/i386/avx2intrin.h: New file. * config/i386/i386-builtin-types.def (PCINT, PCINT64, PV4SI, PV8SI, V32QI_FTYPE_V32QI, V32QI_FTYPE_V16QI, V16HI_FTYPE_V16HI, V16HI_FTYPE_V8HI, V8SI_FTYPE_V8SI, V16HI_FTYPE_V16QI, V8SI_FTYPE_V16QI, V4DI_FTYPE_V16QI, V8SI_FTYPE_V8HI, V4DI_FTYPE_V8HI, V4DI_FTYPE_V4SI, V4DI_FTYPE_PV4DI, V4DI_FTYPE_V2DI, V2DI_FTYPE_PCV2DI_V2DI, V4SI_FTYPE_PCV4SI_V4SI, V32QI_FTYPE_V16HI_V16HI, V16HI_FTYPE_V8SI_V8SI, V32QI_FTYPE_V32QI_V32QI, V16HI_FTYPE_V32QI_V32QI, V16HI_FTYPE_V16HI_V8HI, V16HI_FTYPE_V16HI_V16HI, V16HI_FTYPE_V16HI_INT, V16HI_FTYPE_V16HI_SI, V16HI_FTYPE_V16HI_V16HI_INT, V32QI_FTYPE_V32QI_V32QI_INT, V8SI_FTYPE_V8SI_V4SI, V8SI_FTYPE_V8SI_V8SI, V8SI_FTYPE_V16HI_V16HI, V8SI_FTYPE_V8SI_INT, V8SI_FTYPE_V8SI_SI, V8SI_FTYPE_PCV8SI_V8SI, V4DI_FTYPE_V4DI_V4DI, V4DI_FTYPE_V8SI_V8SI, V4DI_FTYPE_V4DI_V2DI, V4DI_FTYPE_PCV4DI_V4DI, V4DI_FTYPE_V4DI_INT, V2DI_FTYPE_V4DI_INT, V4DI_FTYPE_V4DI_V4DI_INT, V4DI_FTYPE_V4DI_V2DI_INT, VOID_FTYPE_PV2DI_V2DI_V2DI, VOID_FTYPE_PV4DI_V4DI_V4DI, VOID_FTYPE_PV4SI_V4SI_V4SI, VOID_FTYPE_PV8SI_V8SI_V8SI, V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT, V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT, V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT, V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT, V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT, V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT, V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT, V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT, V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT, V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT, V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT, V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT, V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT, V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT, V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT, V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT, V16HI_FTYPE_V16HI_SI_COUNT, V16HI_FTYPE_V16HI_V8HI_COUNT, V8SI_FTYPE_V8SI_SI_COUNT, V8SI_FTYPE_V8SI_V4SI_COUNT, V4DI_FTYPE_V4DI_INT_COUNT, V4DI_FTYPE_V4DI_V2DI_COUNT, V4DI_FTYPE_V4DI_INT_CONVERT, V4DI_FTYPE_V4DI_V4DI_INT_CONVERT): New. * config/i386/i386.c (ix86_builtins): Add IX86_BUILTIN_MPSADBW256, IX86_BUILTIN_PABSB256, IX86_BUILTIN_PABSW256, IX86_BUILTIN_PABSD256, IX86_BUILTIN_PACKSSDW256, IX86_BUILTIN_PACKSSWB256, IX86_BUILTIN_PACKUSDW256, IX86_BUILTIN_PACKUSWB256, IX86_BUILTIN_PADDB256, IX86_BUILTIN_PADDW256, IX86_BUILTIN_PADDD256, IX86_BUILTIN_PADDQ256, IX86_BUILTIN_PADDSB256, IX86_BUILTIN_PADDSW256, IX86_BUILTIN_PADDUSB256, IX86_BUILTIN_PADDUSW256, IX86_BUILTIN_PALIGNR256, IX86_BUILTIN_AND256I, IX86_BUILTIN_ANDNOT256I, IX86_BUILTIN_PAVGB256, IX86_BUILTIN_PAVGW256, IX86_BUILTIN_PBLENDVB256, IX86_BUILTIN_PBLENDVW256, IX86_BUILTIN_PCMPEQB256, IX86_BUILTIN_PCMPEQW256, IX86_BUILTIN_PCMPEQD256, IX86_BUILTIN_PCMPEQQ256, IX86_BUILTIN_PCMPGTB256, IX86_BUILTIN_PCMPGTW256, IX86_BUILTIN_PCMPGTD256, IX86_BUILTIN_PCMPGTQ256, IX86_BUILTIN_PHADDW256, IX86_BUILTIN_PHADDD256, IX86_BUILTIN_PHADDSW256, IX86_BUILTIN_PHSUBW256, IX86_BUILTIN_PHSUBD256, IX86_BUILTIN_PHSUBSW256, IX86_BUILTIN_PMADDUBSW256, IX86_BUILTIN_PMADDWD256, IX86_BUILTIN_PMAXSB256, IX86_BUILTIN_PMAXSW256, IX86_BUILTIN_PMAXSD256, IX86_BUILTIN_PMAXUB256, IX86_BUILTIN_PMAXUW256, IX86_BUILTIN_PMAXUD256, IX86_BUILTIN_PMINSB256, IX86_BUILTIN_PMINSW256, IX86_BUILTIN_PMINSD256, IX86_BUILTIN_PMINUB256, IX86_BUILTIN_PMINUW256, IX86_BUILTIN_PMINUD256, IX86_BUILTIN_PMOVMSKB256, IX86_BUILTIN_PMOVSXBW256, IX86_BUILTIN_PMOVSXBD256, IX86_BUILTIN_PMOVSXBQ256, IX86_BUILTIN_PMOVSXWD256, IX86_BUILTIN_PMOVSXWQ256, IX86_BUILTIN_PMOVSXDQ256, IX86_BUILTIN_PMOVZXBW256, IX86_BUILTIN_PMOVZXBD256, IX86_BUILTIN_PMOVZXBQ256, IX86_BUILTIN_PMOVZXWD256, IX86_BUILTIN_PMOVZXWQ256, IX86_BUILTIN_PMOVZXDQ256, IX86_BUILTIN_PMULDQ256, IX86_BUILTIN_PMULHRSW256, IX86_BUILTIN_PMULHUW256, IX86_BUILTIN_PMULHW256, IX86_BUILTIN_PMULLW256, IX86_BUILTIN_PMULLD256, IX86_BUILTIN_PMULUDQ256, IX86_BUILTIN_POR256, IX86_BUILTIN_PSADBW256, IX86_BUILTIN_PSHUFB256, IX86_BUILTIN_PSHUFD256, IX86_BUILTIN_PSHUFHW256, IX86_BUILTIN_PSHUFLW256, IX86_BUILTIN_PSIGNB256, IX86_BUILTIN_PSIGNW256, IX86_BUILTIN_PSIGND256, IX86_BUILTIN_PSLLDQI256, IX86_BUILTIN_PSLLWI256, IX86_BUILTIN_PSLLW256, IX86_BUILTIN_PSLLDI256, IX86_BUILTIN_PSLLD256, IX86_BUILTIN_PSLLQI256, IX86_BUILTIN_PSLLQ256, IX86_BUILTIN_PSRAWI256, IX86_BUILTIN_PSRAW256, IX86_BUILTIN_PSRADI256, IX86_BUILTIN_PSRAD256, IX86_BUILTIN_PSRLDQI256, IX86_BUILTIN_PSRLWI256, IX86_BUILTIN_PSRLW256, IX86_BUILTIN_PSRLDI256, IX86_BUILTIN_PSRLD256, IX86_BUILTIN_PSRLQI256, IX86_BUILTIN_PSRLQ256, IX86_BUILTIN_PSUBB256, IX86_BUILTIN_PSUBW256, IX86_BUILTIN_PSUBD256, IX86_BUILTIN_PSUBQ256, IX86_BUILTIN_PSUBSB256, IX86_BUILTIN_PSUBSW256, IX86_BUILTIN_PSUBUSB256, IX86_BUILTIN_PSUBUSW256, IX86_BUILTIN_PUNPCKHBW256, IX86_BUILTIN_PUNPCKHWD256, IX86_BUILTIN_PUNPCKHDQ256, IX86_BUILTIN_PUNPCKHQDQ256, IX86_BUILTIN_PUNPCKLBW256, IX86_BUILTIN_PUNPCKLWD256, IX86_BUILTIN_PUNPCKLDQ256, IX86_BUILTIN_PUNPCKLQDQ256, IX86_BUILTIN_PXOR256, IX86_BUILTIN_MOVNTDQA256, IX86_BUILTIN_VBROADCASTSS_PS, IX86_BUILTIN_VBROADCASTSS_PS256, IX86_BUILTIN_VBROADCASTSD_PD256, IX86_BUILTIN_VBROADCASTSI256, IX86_BUILTIN_PBLENDD256, IX86_BUILTIN_PBLENDD128, IX86_BUILTIN_PBROADCASTB256, IX86_BUILTIN_PBROADCASTW256, IX86_BUILTIN_PBROADCASTD256, IX86_BUILTIN_PBROADCASTQ256, IX86_BUILTIN_PBROADCASTB128, IX86_BUILTIN_PBROADCASTW128, IX86_BUILTIN_PBROADCASTD128, IX86_BUILTIN_PBROADCASTQ128, IX86_BUILTIN_VPERMVARSI256, IX86_BUILTIN_VPERMDF256, IX86_BUILTIN_VPERMVARSF256, IX86_BUILTIN_VPERMDI256, IX86_BUILTIN_VPERMTI256, IX86_BUILTIN_VEXTRACT128I256, IX86_BUILTIN_VINSERT128I256, IX86_BUILTIN_MASKLOADD, IX86_BUILTIN_MASKLOADQ, IX86_BUILTIN_MASKLOADD256, IX86_BUILTIN_MASKLOADQ256, IX86_BUILTIN_MASKSTORED, IX86_BUILTIN_MASKSTOREQ, IX86_BUILTIN_MASKSTORED256, IX86_BUILTIN_MASKSTOREQ256, IX86_BUILTIN_PSLLVV4DI, IX86_BUILTIN_PSLLVV2DI, IX86_BUILTIN_PSLLVV8SI, IX86_BUILTIN_PSLLVV4SI, IX86_BUILTIN_PSRAVV8SI, IX86_BUILTIN_PSRAVV4SI, IX86_BUILTIN_PSRLVV4DI, IX86_BUILTIN_PSRLVV2DI, IX86_BUILTIN_PSRLVV8SI, IX86_BUILTIN_PSRLVV4SI, IX86_BUILTIN_GATHERSIV2DF, IX86_BUILTIN_GATHERSIV4DF, IX86_BUILTIN_GATHERDIV2DF, IX86_BUILTIN_GATHERDIV4DF, IX86_BUILTIN_GATHERSIV4SF, IX86_BUILTIN_GATHERSIV8SF, IX86_BUILTIN_GATHERDIV4SF, IX86_BUILTIN_GATHERDIV8SF, IX86_BUILTIN_GATHERSIV2DI, IX86_BUILTIN_GATHERSIV4DI, IX86_BUILTIN_GATHERDIV2DI, IX86_BUILTIN_GATHERDIV4DI, IX86_BUILTIN_GATHERSIV4SI, IX86_BUILTIN_GATHERSIV8SI, IX86_BUILTIN_GATHERDIV4SI, IX86_BUILTIN_GATHERDIV8SI. (bdesc_special_args): Add IX86_BUILTIN_MOVNTDQA256, IX86_BUILTIN_MASKLOADD, IX86_BUILTIN_MASKLOADQ, IX86_BUILTIN_MASKLOADD256, IX86_BUILTIN_MASKLOADQ256, IX86_BUILTIN_MASKSTORED, IX86_BUILTIN_MASKSTOREQ, IX86_BUILTIN_MASKSTORED256, IX86_BUILTIN_MASKSTOREQ256. (bdesc_args): Add IX86_BUILTIN_MPSADBW256, IX86_BUILTIN_PABSB256, IX86_BUILTIN_PABSW256, IX86_BUILTIN_PABSD256, IX86_BUILTIN_PACKSSDW256, IX86_BUILTIN_PACKSSWB256, IX86_BUILTIN_PACKUSDW256, IX86_BUILTIN_PACKUSWB256, IX86_BUILTIN_PADDB256, IX86_BUILTIN_PADDW256, IX86_BUILTIN_PADDD256, IX86_BUILTIN_PADDQ256, IX86_BUILTIN_PADDSB256, IX86_BUILTIN_PADDSW256, IX86_BUILTIN_PADDUSB256, IX86_BUILTIN_PADDUSW256, IX86_BUILTIN_PALIGNR256, IX86_BUILTIN_AND256I, IX86_BUILTIN_ANDNOT256I, IX86_BUILTIN_PAVGB256, IX86_BUILTIN_PAVGW256, IX86_BUILTIN_PBLENDVB256, IX86_BUILTIN_PBLENDVW256, IX86_BUILTIN_PCMPEQB256, IX86_BUILTIN_PCMPEQW256, IX86_BUILTIN_PCMPEQD256, IX86_BUILTIN_PCMPEQQ256, IX86_BUILTIN_PCMPGTB256, IX86_BUILTIN_PCMPGTW256, IX86_BUILTIN_PCMPGTD256, IX86_BUILTIN_PCMPGTQ256, IX86_BUILTIN_PHADDW256, IX86_BUILTIN_PHADDD256, IX86_BUILTIN_PHADDSW256, IX86_BUILTIN_PHSUBW256, IX86_BUILTIN_PHSUBD256, IX86_BUILTIN_PHSUBSW256, IX86_BUILTIN_PMADDUBSW256, IX86_BUILTIN_PMADDWD256, IX86_BUILTIN_PMAXSB256, IX86_BUILTIN_PMAXSW256, IX86_BUILTIN_PMAXSD256, IX86_BUILTIN_PMAXUB256, IX86_BUILTIN_PMAXUW256, IX86_BUILTIN_PMAXUD256, IX86_BUILTIN_PMINSB256, IX86_BUILTIN_PMINSW256, IX86_BUILTIN_PMINSD256, IX86_BUILTIN_PMINUB256, IX86_BUILTIN_PMINUW256, IX86_BUILTIN_PMINUD256, IX86_BUILTIN_PMOVMSKB256, IX86_BUILTIN_PMOVSXBW256, IX86_BUILTIN_PMOVSXBD256, IX86_BUILTIN_PMOVSXBQ256, IX86_BUILTIN_PMOVSXWD256, IX86_BUILTIN_PMOVSXWQ256, IX86_BUILTIN_PMOVSXDQ256, IX86_BUILTIN_PMOVZXBW256, IX86_BUILTIN_PMOVZXBD256, IX86_BUILTIN_PMOVZXBQ256, IX86_BUILTIN_PMOVZXWD256, IX86_BUILTIN_PMOVZXWQ256, IX86_BUILTIN_PMOVZXDQ256, IX86_BUILTIN_PMULDQ256, IX86_BUILTIN_PMULHRSW256, IX86_BUILTIN_PMULHUW256, IX86_BUILTIN_PMULHW256, IX86_BUILTIN_PMULLW256, IX86_BUILTIN_PMULLD256, IX86_BUILTIN_PMULUDQ256, IX86_BUILTIN_POR256, IX86_BUILTIN_PSADBW256, IX86_BUILTIN_PSHUFB256, IX86_BUILTIN_PSHUFD256, IX86_BUILTIN_PSHUFHW256, IX86_BUILTIN_PSHUFLW256, IX86_BUILTIN_PSIGNB256, IX86_BUILTIN_PSIGNW256, IX86_BUILTIN_PSIGND256, IX86_BUILTIN_PSLLDQI256, IX86_BUILTIN_PSLLWI256, IX86_BUILTIN_PSLLW256, IX86_BUILTIN_PSLLDI256, IX86_BUILTIN_PSLLD256, IX86_BUILTIN_PSLLQI256, IX86_BUILTIN_PSLLQ256, IX86_BUILTIN_PSRAWI256, IX86_BUILTIN_PSRAW256, IX86_BUILTIN_PSRADI256, IX86_BUILTIN_PSRAD256, IX86_BUILTIN_PSRLDQI256, IX86_BUILTIN_PSRLWI256, IX86_BUILTIN_PSRLW256, IX86_BUILTIN_PSRLDI256, IX86_BUILTIN_PSRLD256, IX86_BUILTIN_PSRLQI256, IX86_BUILTIN_PSRLQ256, IX86_BUILTIN_PSUBB256, IX86_BUILTIN_PSUBW256, IX86_BUILTIN_PSUBD256, IX86_BUILTIN_PSUBQ256, IX86_BUILTIN_PSUBSB256, IX86_BUILTIN_PSUBSW256, IX86_BUILTIN_PSUBUSB256, IX86_BUILTIN_PSUBUSW256, IX86_BUILTIN_PUNPCKHBW256, IX86_BUILTIN_PUNPCKHWD256, IX86_BUILTIN_PUNPCKHDQ256, IX86_BUILTIN_PUNPCKHQDQ256, IX86_BUILTIN_PUNPCKLBW256, IX86_BUILTIN_PUNPCKLWD256, IX86_BUILTIN_PUNPCKLDQ256, IX86_BUILTIN_PUNPCKLQDQ256, IX86_BUILTIN_PXOR256, IX86_BUILTIN_VBROADCASTSS_PS, IX86_BUILTIN_VBROADCASTSS_PS256, IX86_BUILTIN_VBROADCASTSD_PD256, IX86_BUILTIN_VBROADCASTSI256, IX86_BUILTIN_PBLENDD256, IX86_BUILTIN_PBLENDD128, IX86_BUILTIN_PBROADCASTB256, IX86_BUILTIN_PBROADCASTW256, IX86_BUILTIN_PBROADCASTD256, IX86_BUILTIN_PBROADCASTQ256, IX86_BUILTIN_PBROADCASTB128, IX86_BUILTIN_PBROADCASTW128, IX86_BUILTIN_PBROADCASTD128, IX86_BUILTIN_PBROADCASTQ128, IX86_BUILTIN_VPERMVARSI256, IX86_BUILTIN_VPERMDF256, IX86_BUILTIN_VPERMVARSF256, IX86_BUILTIN_VPERMDI256, IX86_BUILTIN_VPERMTI256, IX86_BUILTIN_VEXTRACT128I256, IX86_BUILTIN_VINSERT128I256, IX86_BUILTIN_PSLLVV4DI, IX86_BUILTIN_PSLLVV2DI, IX86_BUILTIN_PSLLVV8SI, IX86_BUILTIN_PSLLVV4SI, IX86_BUILTIN_PSRAVV8SI, IX86_BUILTIN_PSRAVV4SI, IX86_BUILTIN_PSRLVV4DI, IX86_BUILTIN_PSRLVV2DI, IX86_BUILTIN_PSRLVV8SI, IX86_BUILTIN_PSRLVV4SI. (ix86_init_mmx_sse_builtins): Add IX86_BUILTIN_GATHERSIV2DF, IX86_BUILTIN_GATHERSIV4DF, IX86_BUILTIN_GATHERDIV2DF, IX86_BUILTIN_GATHERDIV4DF, IX86_BUILTIN_GATHERSIV4SF, IX86_BUILTIN_GATHERSIV8SF, IX86_BUILTIN_GATHERDIV4SF, IX86_BUILTIN_GATHERDIV8SF, IX86_BUILTIN_GATHERSIV2DI, IX86_BUILTIN_GATHERSIV4DI, IX86_BUILTIN_GATHERDIV2DI, IX86_BUILTIN_GATHERDIV4DI, IX86_BUILTIN_GATHERSIV4SI, IX86_BUILTIN_GATHERSIV8SI, IX86_BUILTIN_GATHERDIV4SI, IX86_BUILTIN_GATHERDIV8SI. (ix86_preferred_simd_mode): Support AVX2 modes. (ix86_expand_args_builtin): Support AVX2 built-ins. (ix86_expand_special_args_builtin): Likewise. (ix86_expand_builtin): Likewise. * config/i386/i386.md (UNSPEC_VPERMSI): New. (UNSPEC_VPERMDF): Likewise. (UNSPEC_VPERMSF): Likewise. (UNSPEC_VPERMDI): Likewise. (UNSPEC_VPERMTI): Likewise. (UNSPEC_GATHER): Likewise. (ssemodesuffix): Extend. * config/i386/immintrin.h: Include avx2intrin.h when __AVX2__ is defined. * config/i386/predicates.md (const1248_operand): New. * config/i386/sse.md (VI_AVX2): (VI1_AVX2): Likewise. (VI2_AVX2): Likewise. (VI4_AVX2): Likewise. (VI8_AVX2): Likewise. (VIMAX_AVX2): Likewise. (SSESCALARMODE): Likewise. (VI12_AVX2): Likewise. (VI24_AVX2): Likewise. (VI124_AVX2): Likeuse_submit_for_speed = 1 wise. (VI248_AVX2): Likewise. (VI48_AVX2): Likewise. (VI4SD_AVX2): Likewise. (V48_AVX2): Likewise. (avx2modesuffix): Likewise. (sse_avx2): Likewise. (sse2_avx2): Likewise. (ssse3_avx2): Likewise. (sse4_1_avx2): Likewise. (avx_avx2): Likewise. (lshift)<code_oterator>: Likewise. (lshift_insn): Likewise. (lshift)<code_attr>: Likewise. (SSESHORTMODE): Likewise. (SSELONGMODE): Likewise. (SSEBYTEMODE): Likewise. (AVXTOSSEMODE): Likewise. (shortmode): Likewise. (ssescalarmodesuffix): Update. (sseunpackmode): Likewise. (ssepackmode): Likewise. (AVX256MODEI): New. (AVX256MODE124): Likewise. (AVX256MODE1248): Likewise. (AVX256MODE248): Likewise. (AVXMODE48P_SI): Likewise. (AVXMODE48P_SI): Likewise. (AVXMODE48P_DI): Likewise. (AVXMODE48P_DI): Likewise. (gthrfirstp): Likewise. (gthrlastp): Likewise. (avx2): Likwise. (ssevecsize): Likewise. (ssedoublesizemode): Likewise. (avxvecmode): Likewise. (avxvecsize): Likewise. (avxhalfvecmode): Likewise. (avxscalarmode): Likewise. (avxpermvecmode): Likewise. (avxmodesuffixp): Likewise. (avxmodesuffix): Likewise. (avx2_vec_dupv4sf): New. (avx2_vec_dupv8sf): Likewise. (avx2_interleave_highv4di): Likewise. (avx2_interleave_lowv4di): Likewise. (<plusminus_insn><mode>3): Update. (*<plusminus_insn><mode>3): Likewise. (sse2_<plusminus_insn><mode>3): Rename to ... ("<sse2_avx2>_<plusminus_insn><mode>3): ... this. updated. (*sse2_<plusminus_insn><mode>3): Likewise. (*<sse2_avx2>_<plusminus_insn><mode>3): Likewise. (mulv8hi3): Likewise. (mul<mode>3): Likewise. (*mulv8hi3): Likewise. (*mul<mode>3): Likewise. (<s>mulv8hi3_highpart): Likewise. (<s>mul<mode>3_highpart): Likewise. (*<s>mulv8hi3_highpart): Likewise. (*<s>mul<mode>3_highpart): Likewise. (avx2_umulv4siv4di3): Likewise. (*avx_umulv4siv4di3): Likewise. (sse4_1_mulv2siv2di3): Likewise. (<sse4_1_avx2>_mul<shortmode><mode>3): Likewise. (*sse4_1_mulv2siv2di3): Likewise. (*<sse4_1_avx2>_mulv2siv2di3): Likewise. (avx2_pmaddwd): New. (*avx2_pmaddwd): Likewise. (mulv4si3): Rename to ... (mul<mode>3): ... this. Update. (*sse4_1_mulv4si3): Likewise. (*<sse4_1_avx2>_mul<mode>3): Likewise. (ashr<mode>3): Update. (avx2_lshrqv4di3): New. (lshr<mode>3): Update. (avx2_lshlqv4di3): New. (avx2_lshl<mode>3): Likewise. (sse2_ashlv1ti3): Rename to ... (<sse2_avx2>_ashl<mode>3): ... this. Update. (avx2_<code><mode>3)<umaxmin>: New. (*avx2_<code><mode>3)<umaxmin>: Likewise. (avx2_<code><mode>3)<smaxmin>: New. (*avx2_<code><mode>3)<smaxmin>: Likewise. (avx2_eq<mode>3): Likewise. (*avx2_eq<mode>3): Likewise. (avx2_gt<mode>3): Likewise. (sse2_andnot<mode>3): Rename to ... (<sse2_avx2>_andnot<mode>3): ... this. Update. (*andnot<mode>3): Update. (<code><mode>3)<any_logic>: Update. (*<code><mode>3)<any_logic>: Likewise. (sse2_packsswb): Rename to ... (<sse2_avx2>_packsswb): ... this. Update. (sse2_packssdw): Likewise. (<sse2_avx2>_packssdw): Likewise. (sse2_packuswb): Likewise. (<sse2_avx2>_packuswb): Likewise. (avx2_interleave_highv32qi): New. (avx2_interleave_lowv32qi): Likewise. (avx2_interleave_highv16hi): Likewise. (avx2_interleave_lowv16hi): Likewise. (avx2_interleave_highv8si): Likewise. (avx2_interleave_lowv8si): Likewise. (avx2_pshufd): New (avx2_pshufd_1): Likewise. (avx2_pshuflwv3): Likewise. (avx2_pshuflw_1): Likewise. (avx2_pshufhwv3): Likewise. (avx2_pshufhw_1): Likewise. (avx2_uavgv32qi3): Likewise. (*avx2_uavgv32qi3): Likewise. (avx2_uavgv16hi3): Likewise. (*avx2_uavgv16hi3): Likewise. (sse2_psadbw): Rename to ... (<sse2_avx2>_psadbw): ... this. Update. (avx2_pmovmskb): New. (avx2_phaddwv16hi3): Likewise. (avx2_phadddv8si3): Likewise. (avx2_phaddswv16hi3): Likewise. (avx2_phsubwv16hi3): Likewise. (avx2_phsubdv8si3): Likewise. (avx2_phsubswv16hi3): Likewise. (avx2_pmaddubsw256): Likewise. (avx2_umulhrswv16hi3): Likewise. (*avx2_umulhrswv16hi3): Likewise. (ssse3_pshufbv16qi3): Rename to ... (<ssse3_avx2>_pshufb<mode>3): ... this. Update. (ssse3_psign<mode>3): Likewise. (<ssse3_avx2>_psign<mode>3): Likewise. (ssse3_palignrti): Likewise. (<ssse3_avx2>_palignr<mode>): Likewise. (abs<mode>2): Likewise. (sse4_1_movntdqa): Rename to ... (<sse4_1_avx2>_movntdqa): ... this. Update. (sse4_1_mpsadbw): Likewise. (<sse4_1_avx2>_mpsadbw): Likewise. (avx2_packusdw): New. (sse4_1_pblendvb): Rename to ... (<sse4_1_avx2>_pblendvb): ... this. Update. (sse4_1_pblendw): Likewise. (<sse4_1_avx2>_pblendw): Likewise. (avx2_pblendd<mode>): New. (avx2_<code>v16qiv16hi2): Likewise. (avx2_<code>v8qiv8si2): Likewise. (avx2_<code>v8hiv8si2): Likewise. (avx2_<code>v4qiv4di2): Likewise. (avx2_<code>v4hiv4di2): Likewise. (avx2_<code>v4siv4di2): Likewise. (avx2_pbroadcast<mode>): Likewise. (avx2_permvarv8si): Likewise. (avx2_permv4df): Likewise. (avx2_permvarv8sf): Likewise. (avx2_permv4di): Likewise. (avx2_permv2ti): Likewise. (avx2_vec_dupv4df): Likewise. (avx2_vbroadcasti128_<mode>): Likewise. (avx2_vec_set_lo_v4di): Likewise. (avx2_vec_set_hi_v4di): Likewise. (avx_maskload<ssemodesuffix><avxsizesuffix>): Rename to ... (<avx_avx2>_maskload<avx2modesuffix><avxmodesuffix>): ... this. Update. (avx_maskstore<ssemodesuffix><avxsizesuffix>): Likewise. (<avx_avx2>_maskstore<avx2modesuffix><avxmodesuffix>): Likewise. (*avx2_maskmov<avx2modesuffix><avxmodesuffix>): New. (avx2_extracti128): Likewise. (avx2_inserti128): Likewise. (avx2_ashrvv8si): Likewise. (avx2_ashrvv4si): Likewise. (avx2_<lshift>vv8si): Likewise. (avx2_<lshift>v<mode>): Likewise. (avx2_<lshift>vv2di): Likewise. (avx2_gathersi<mode>): Likewise. (*avx2_gathersi<mode>): Likewise. (avx2_gatherdi<mode>): Likewise. (*avx2_gatherdi<mode>): Likewise. (avx2_gatherdi<mode>256): Likewise. (*avx2_gatherdi<mode>256): Likewise. * doc/extend.texi: Document AVX2 built-in functions. * doc/invoke.texi: Document -mavx2. From-SVN: r177955
2011-08-20tm.texi.in (PREFERRED_OUTPUT_RELOAD_CLASS): Remove.Anatoly Sokolov2-18/+0
* doc/tm.texi.in (PREFERRED_OUTPUT_RELOAD_CLASS): Remove. * doc/tm.texi: Regenerate. * targhooks.c (default_preferred_output_reload_class): Don't use PREFERRED_OUTPUT_RELOAD_CLASS macro. * system.h (PREFERRED_OUTPUT_RELOAD_CLASS): Poison. From-SVN: r177926
2011-08-19c-parser.c (c_parser_postfix_expression): Handle RID_BUILTIN_COMPLEX.Joseph Myers1-0/+12
* c-parser.c (c_parser_postfix_expression): Handle RID_BUILTIN_COMPLEX. * doc/extend.texi (__builtin_complex): Document. c-family: * c-common.c (c_common_reswords): Add __builtin_complex. * c-common.h (RID_BUILTIN_COMPLEX): New. testsuite: * gcc.dg/builtin-complex-err-1.c, gcc.dg/builtin-complex-err-2.c, gcc.dg/dfp/builtin-complex.c, gcc.dg/torture/builtin-complex-1.c: New tests. From-SVN: r177911
2011-08-18Add -mavx2.Kirill Yukhin1-2/+4
2011-08-18 Kirill Yukhin <kirill.yukhin@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX2_SET): New. (OPTION_MASK_ISA_AVX_UNSET): Update. (OPTION_MASK_ISA_AVX2_UNSET): New. (ix86_handle_option): Handle OPT_mavx2 case. * config/i386/cpuid.h (bit_AVX2): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect AVX2 feature. * config/i386/i386-c.c (ix86_target_macros_internal): Conditionally define __AVX2__. * config/i386/i386.c (ix86_option_override_internal): Define PTA_AVX2. Define "core-avx2" processor alias. Handle avx2 option. (ix86_valid_target_attribute_inner_p): Handle avx2 option. * config/i386/i386.h (TARGET_AVX2): New. * config/i386/i386.opt (mavx2): New. * doc/invoke.texi: Document -mavx2. From-SVN: r177876
2011-08-18Keep tm, div_t, ldiv_t, lconv mangling on Solaris (PR libstdc++-v3/1773)Rainer Orth1-0/+4
Co-Authored-By: Marc Glisse <marc.glisse@normalesup.org> From-SVN: r177863
2011-08-18tm.texi.in (TARGET_RTX_COSTS): Add an opno paramter.Richard Sandiford2-9/+19
gcc/ * doc/tm.texi.in (TARGET_RTX_COSTS): Add an opno paramter. * doc/tm.texi: Regenerate. * target.def (rtx_costs): Add an opno parameter. * hooks.h (hook_bool_rtx_int_int_intp_bool_false): Replace with... (hook_bool_rtx_int_int_int_intp_bool_false): ...this. * hooks.c (hook_bool_rtx_int_int_intp_bool_false): Replace with... (hook_bool_rtx_int_int_int_intp_bool_false): ...this. * cse.c (COST_IN): Add an opno parameter. (notreg_cost): Likewise. Update call to rtx_cost. (COST, fold_rtx): Update accordingly. * dojump.c (prefer_and_bit_test): Update call to rtx_cost. * expmed.c (emit_store_flag): Likewise. * optabs.c (avoid_expensive_constant): Add an opno parameter. Update call to rtx_cost. (expand_binop_directly, expand_binop): Likewise. (expand_twoval_binop, prepare_cmp_insn): Likewise. * rtl.h (rtx_cost, get_full_rtx_cost): Add opno parameters. (set_src_cost, get_full_set_src_cost): Update accordingly. * rtlanal.c (rtx_cost): Add an opno parameter. Update call to target hook. (get_full_rtx_cost): Add an opno paramter. Update calls to rtx_cost. (default_adress_cost): Update calls to rtx_cost. * config/arm/arm.c (arm_rtx_costs_1, arm_size_rtx_costs) (arm_slowmul_rtx_costs): Adjust calls to rtx_cost. (arm_rtx_costs): Add an opno parameter. * config/alpha/alpha.c (alpha_rtx_costs): Add an opno parameter and adjust any recursive rtx-cost calls. * config/avr/avr.c (avr_operand_rtx_cost, avr_rtx_costs): Likewise. * config/bfin/bfin.c (bfin_rtx_costs): Likewise. * config/c6x/c6x.c (c6x_rtx_costs): Likewise. * config/cris/cris.c (cris_rtx_costs): Likewise. * config/frv/frv.c (frv_rtx_costs): Likewise. * config/h8300/h8300.c (h8300_rtx_costs): Likewise. * config/i386/i386.c (ix86_rtx_costs): Likewise. * config/ia64/ia64.c (ia64_rtx_costs): Likewise. * config/iq2000/iq2000.c (iq2000_rtx_costs): Likewise. * config/lm32/lm32.c (lm32_rtx_costs): Likewise. * config/m32c/m32c.c (m32c_rtx_costs): Likewise. * config/m32r/m32r.c (m32r_rtx_costs): Likewise. * config/m68k/m68k.c (m68k_rtx_costs): Likewise. * config/mcore/mcore.c (mcore_rtx_costs): Likewise. * config/mep/mep.c (mep_rtx_cost): Likewise. * config/microblaze/microblaze.c (microblaze_rtx_costs): Likewise. * config/mips/mips.c (mips_binary_cost): Update call to rtx_cost. (mips_zero_extend_cost): Add an opno parameter. * config/mmix/mmix.c (mmix_rtx_costs): Likewise. * config/mn10300/mn10300.c (mn10300_address_cost): Update call to rtx_cost. (mn10300_rtx_costs): Add an opno parameter and adjust any recursive rtx-cost calls. * config/pa/pa.c (hppa_rtx_costs): Likewise. * config/pdp11/pdp11.c (pdp11_rtx_costs): Likewise. * config/picochip/picochip.c (picochip_rtx_costs): Likewise. * config/rs6000/rs6000.c (rs6000_rtx_costs): Likewise. (rs6000_debug_rtx_costs): Likewise. * config/s390/s390.c (s390_rtx_costs): Likewise. * config/score/score-protos.h (score_rtx_costs): Likewise. * config/score/score.c (score_rtx_costs): Likewise. * config/sh/sh.c (andcosts): Update call to rtx_cost. (sh_rtx_costs): Add an opno parameter. * config/sparc/sparc.c (sparc_rtx_costs): Likewise. * config/spu/spu.c (spu_rtx_costs): Likewise. * config/stormy16/stormy16.c (xstormy16_rtx_costs): Likewise. * config/v850/v850.c (v850_rtx_costs): Likewise. * config/vax/vax.c (vax_rtx_costs): Likewise. * config/xtensa/xtensa.c (xtensa_rtx_costs): Likewise. From-SVN: r177852
2011-08-16pt.c (instantiate_class_template_1): If DECL_PRESERVE_P is set on a member ↵Jason Merrill1-0/+8
function or static data member... * pt.c (instantiate_class_template_1): If DECL_PRESERVE_P is set on a member function or static data member, call mark_used. From-SVN: r177811
2011-08-12builtins.c (expand_builtin_memcmp): Do not use cmpstrnsi pattern.Nick Clifton1-7/+11
* builtins.c (expand_builtin_memcmp): Do not use cmpstrnsi pattern. * doc/md.texi (cmpstrn): Note that the comparison stops if both fetched bytes are zero. (cmpstr): Likewise. (cmpmem): Note that the comparison does not stop if both of the fetched bytes are zero. From-SVN: r177701
2011-08-11plugin.def: Add event for finish_decl.Romain Geissler1-0/+1
2011-08-11 Romain Geissler <romain.geissler@gmail.com> Brian Hackett <bhackett1024@gmail.com> gcc/ChangeLog: * plugin.def: Add event for finish_decl. * plugin.c (register_callback, invoke_plugin_callbacks): Same. * c-decl.c (finish_decl): Invoke callbacks on above event. * doc/plugins.texi: Document above event. gcc/cp/ChangeLog: * decl.c (cp_finish_decl): Invoke callbacks on finish_decl event. gcc/testsuite/ChangeLog: * g++.dg/plugin/decl_plugin.c: New. * g++.dg/plugin/decl-plugin-test.C: New. * g++.dg/plugin/plugin.exp: Add above testcase. Co-Authored-By: Brian Hackett <bhackett1024@gmail.com> From-SVN: r177674
2011-08-11md.texi (define_bypass): Say that the instruction names can be ↵Richard Sandiford1-2/+10
filename-style globs. gcc/ * doc/md.texi (define_bypass): Say that the instruction names can be filename-style globs. * Makefile.in (FNMATCH_H): Define. (build/genattrtab.o, build/genautomata.o): Depend on $(FNMATCH_H). * genattrtab.c: Include fnmatch.h. (bypass_list): Change field name from "insn" to "pattern". (gen_bypass_1): Update accordingly. (process_bypasses): Use fnmatch to check for matches between insn reservations and define_bypasses. * genautomata.c: Include fnmatch.h. (bypass_decl): Rename in_insn_name and out_insn_name to in_pattern and out_pattern respectively. (gen_bypass, insert_bypass): Update accordingly. (for_each_matching_insn, process_bypass_2, process_bypass_1) (process_bypass): New functions. (process_decls): Use process_bypass. Update after field name changes. From-SVN: r177649
generated by cgit v1.1 at 2024-08-22 18:19:51 +0000