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author | David S. Miller <davem@davemloft.net> | 2011-09-30 07:54:07 +0000 |
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committer | David S. Miller <davem@gcc.gnu.org> | 2011-09-30 00:54:07 -0700 |
commit | c4728c6b20436826e469927a76fa12b89f7cf11e (patch) | |
tree | ef2752591fdb528a5b9df11ad312ebf11a2712dd /gcc/doc | |
parent | 3aaedee02143cb24a313a147f787d4211844a042 (diff) | |
download | gcc-c4728c6b20436826e469927a76fa12b89f7cf11e.zip gcc-c4728c6b20436826e469927a76fa12b89f7cf11e.tar.gz gcc-c4728c6b20436826e469927a76fa12b89f7cf11e.tar.bz2 |
Add sparc VIS 2.0 builtins, intrinsics, and option to control them.
gcc/
* config/sparc/sparc.opt (VIS2): New option.
* doc/invoke.texi: Document it.
* config/sparc/sparc.md (UNSPEC_EDGE8N, UNSPEC_EDGE8LN,
UNSPEC_EDGE16N, UNSPEC_EDGE16LN, UNSPEC_EDGE32N,
UNSPEC_EDGE32LN, UNSPEC_BSHUFFLE): New unspecs.
(define_attr type): New insn type 'edgen'.
(bmask<P:mode>_vis, bshuffle<V64I:mode>_vis, edge8n<P:mode>_vis,
edge8ln<P:mode>_vis, edge16n<P:mode>_vis, edge16ln<P:mode>_vis,
edge32n<P:mode>_vis, edge32ln<P:mode>_vis): New insn VIS 2.0
patterns.
* niagara.md: Handle edgen.
* niagara2.md: Likewise.
* ultra1_2.md: Likewise.
* ultra3.md: Likewise.
* config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__
to 0x200 when TARGET_VIS2.
* config/sparc/sparc.c (sparc_option_override): Set MASK_VIS2 by
default when targetting capable cpus. TARGET_VIS2 implies
TARGET_VIS, clear and it when TARGET_FPU is disabled.
(sparc_vis_init_builtins): Emit new VIS 2.0 builtins.
(sparc_expand_builtin): Fix predicate indexing when builtin returns
void.
(sparc_fold_builtin): Do not eliminate bmask when result is ignored.
* config/sparc/visintrin.h (__vis_bmask, __vis_bshuffledi,
__vis_bshufflev2si, __vis_bshufflev4hi, __vis_bshufflev8qi,
__vis_edge8n, __vis_edge8ln, __vis_edge16n, __vis_edge16ln,
__vis_edge32n, __vis_edge32ln): New VIS 2.0 interfaces.
* doc/extend.texi: Document new VIS 2.0 builtins.
gcc/testsuite/
* gcc.target/sparc/bmaskbshuf.c: New test.
* gcc.target/sparc/edgen.c: New test.
From-SVN: r179376
Diffstat (limited to 'gcc/doc')
-rw-r--r-- | gcc/doc/extend.texi | 18 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 12 |
2 files changed, 29 insertions, 1 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index e8a777d..7ca50da 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -13016,6 +13016,24 @@ long __builtin_vis_array16 (long, long); long __builtin_vis_array32 (long, long); @end smallexample +Additionally, when you use the @option{-mvis2} switch, the VIS version +2.0 built-in functions become available: + +@smallexample +long __builtin_vis_bmask (long, long); +int64_t __builtin_vis_bshuffledi (int64_t, int64_t); +v2si __builtin_vis_bshufflev2si (v2si, v2si); +v4hi __builtin_vis_bshufflev2si (v4hi, v4hi); +v8qi __builtin_vis_bshufflev2si (v8qi, v8qi); + +long __builtin_vis_edge8n (void *, void *); +long __builtin_vis_edge8ln (void *, void *); +long __builtin_vis_edge16n (void *, void *); +long __builtin_vis_edge16ln (void *, void *); +long __builtin_vis_edge32n (void *, void *); +long __builtin_vis_edge32ln (void *, void *); +@end smallexample + @node SPU Built-in Functions @subsection SPU Built-in Functions diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e166964..0ce15ff 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -880,7 +880,7 @@ See RS/6000 and PowerPC Options. -mstack-bias -mno-stack-bias @gol -munaligned-doubles -mno-unaligned-doubles @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol --mfmaf -mno-fmaf} +-mvis2 -mno-vis2 -mfmaf -mno-fmaf} @emph{SPU Options} @gccoptlist{-mwarn-reloc -merror-reloc @gol @@ -17430,6 +17430,16 @@ mode for all SPARC-V9 processors. With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC Visual Instruction Set extensions. The default is @option{-mno-vis}. +@item -mvis2 +@itemx -mno-vis2 +@opindex mvis2 +@opindex mno-vis2 +With @option{-mvis2}, GCC generates code that takes advantage of +version 2.0 of the UltraSPARC Visual Instruction Set extensions. The +default is @option{-mvis2} when targetting a cpu that supports such +instructions, such as UltraSPARC-III and later. Setting @option{-mvis2} +also sets @option{-mvis}. + @item -mfmaf @itemx -mno-fmaf @opindex mfmaf |