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| author | Richard Guenther <rguenther@suse.de> | 2011-09-02 13:53:32 +0000 |
|---|---|---|
| committer | Richard Biener <rguenth@gcc.gnu.org> | 2011-09-02 13:53:32 +0000 |
| commit | e9e1d143b5ea00f99191cd0e65c09ee972ebcedb (patch) | |
| tree | a60e543826617c5a8adf334f075bb61da4cc0003 /gcc/doc | |
| parent | aa547a51dab42285a259b77d45bec65fa3f82646 (diff) | |
| download | gcc-e9e1d143b5ea00f99191cd0e65c09ee972ebcedb.zip gcc-e9e1d143b5ea00f99191cd0e65c09ee972ebcedb.tar.gz gcc-e9e1d143b5ea00f99191cd0e65c09ee972ebcedb.tar.bz2 | |
re PR tree-optimization/27460 (Does not vectorize statements with mixed type COND_EXPRs)
2011-09-02 Richard Guenther <rguenther@suse.de>
PR tree-optimization/27460
PR middle-end/29269
* doc/md.texi (vcond): Document.
* genopinit.c (optabs): Turn vcond{,u}_optab into a conversion
optab with two modes.
* optabs.h (enum convert_optab_index): Add COI_vcond, COI_vcondu.
(enum direct_optab_index): Remove DOI_vcond, DOI_vcondu.
(vcond_optab): Adjust.
(vcondu_optab): Likewise.
(expand_vec_cond_expr_p): Adjust prototype.
* optabs.c (get_vcond_icode): Adjust.
(expand_vec_cond_expr_p): Likewise.
(expand_vec_cond_expr): Likewise.
* tree-vect-stmts.c (vect_is_simple_cond): Return the comparison
vector type.
(vectorizable_condition): Allow differing types for comparison
and result.
* config/i386/i386.c (ix86_expand_sse_cmp): Use proper mode
for the comparison.
* config/i386/sse.md (vcond<mode>): Split to
vcond<V_256:mode><VF_256:mode>, vcond<V_128:mode><VF_128:mode>,
vcond<V_128:mode><VI124_128:mode> and
vcondu<V_128:mode><VI124_128:mode>.
(vcondv2di): Change to vcond<VI8F_128:mode>v2di.
(vconduv2di): Likewise.
* config/arm/neon.md (vcond<mode>): Change to vcond*<mode><mode>.
(vcondu<mode>): Likewise.
* config/ia64/vect.md (vcond<mode>): Likewise.
(vcondu<mode>): Likewise.
(vcondv2sf): Likewise.
* config/mips/mips-ps-3d.md (vcondv2sf): Likewise.
* config/rs6000/paired.md (vcondv2sf): Likewise.
* config/rs6000/vector.md (vcond<mode>): Likewise.
(vcondu<mode>): Likewise.
* config/spu/spu.md (vcond<mode>): Likewise.
(vcondu<mode>): Likewise.
* gcc.dg/vect/vect-cond-7.c: New testcase.
From-SVN: r178480
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/md.texi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7fc1a5e..1aa8552 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4017,6 +4017,17 @@ and input vectors should have the same modes (@code{N} elements). The low Initialize the vector to given values. Operand 0 is the vector to initialize and operand 1 is parallel containing values for individual fields. +@cindex @code{vcond@var{m}@var{n}} instruction pattern +@item @samp{vcond@var{m}@var{n}} +Output a conditional vector move. Operand 0 is the destination to +receive a combination of operand 1 and operand 2, which are of mode @var{m}, +dependent on the outcome of the predicate in operand 3 which is a +vector comparison with operands of mode @var{n} in operands 4 and 5. The +modes @var{m} and @var{n} should have the same size. Operand 0 +will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk} +where @var{msk} is computed by element-wise evaluation of the vector +comparison with a truth value of all-ones and a false value of all-zeros. + @cindex @code{push@var{m}1} instruction pattern @item @samp{push@var{m}1} Output a push instruction. Operand 0 is value to push. Used only when |