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| author | David S. Miller <davem@davemloft.net> | 2011-09-25 21:28:51 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 2011-09-25 14:28:51 -0700 |
| commit | e8b141b593cea20857b5041b4c4f1139e7c67712 (patch) | |
| tree | bed5b88ace72ee9f25edf67d046c725807af7b3a /gcc/doc | |
| parent | 7cbcf85bf976f8eaeb2beee113b1ea60bdb39f99 (diff) | |
| download | gcc-e8b141b593cea20857b5041b4c4f1139e7c67712.zip gcc-e8b141b593cea20857b5041b4c4f1139e7c67712.tar.gz gcc-e8b141b593cea20857b5041b4c4f1139e7c67712.tar.bz2 | |
Add support for floating-point fused multiply-add on Sparc.
* configure.ac: Add feature check to make sure the assembler
supports the FMAF, HPC, and VIS 3.0 instructions found on
Niagara-3 and later cpus.
* configure: Rebuild.
* config.in: Likewise.
* config/sparc/sparc.opt: New option '-mfmaf'.
* config/sparc/sparc.md: Add float fused multiply-add patterns.
* config/sparc/sparc.h (AS_NIAGARA3_FLAG): New macro.
(ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Use it, as needed.
* config/sparc/sol2.h (ASM_CPU32_DEFAULT_SPEC,
ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Likewise.
* config/sparc/sparc.c (sparc_option_override): Turn MASK_FMAF on
by default for Niagara-3 and later. Turn it off if TARGET_FPU is
disabled.
(sparc_rtx_costs): Handle 'FMA'.
* doc/invoke.texi: Document -mfmaf.
From-SVN: r179174
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 957d75c..1f04612 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -879,7 +879,8 @@ See RS/6000 and PowerPC Options. -mlittle-endian @gol -mstack-bias -mno-stack-bias @gol -munaligned-doubles -mno-unaligned-doubles @gol --mv8plus -mno-v8plus -mvis -mno-vis} +-mv8plus -mno-v8plus -mvis -mno-vis @gol +-mfmaf -mno-fmaf} @emph{SPU Options} @gccoptlist{-mwarn-reloc -merror-reloc @gol @@ -17397,6 +17398,15 @@ mode for all SPARC-V9 processors. @opindex mno-vis With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC Visual Instruction Set extensions. The default is @option{-mno-vis}. + +@item -mfmaf +@itemx -mno-fmaf +@opindex mfmaf +@opindex mno-fmaf +With @option{-mfmaf}, GCC generates code that takes advantage of the UltraSPARC +Fused Multiply-Add Floating-point extensions. The default is @option{-mfmaf} +when targetting a cpu that supports such instructions, such as Niagara-3 and +later. @end table These @samp{-m} options are supported in addition to the above |