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2023-06-15LoongArch: Set default alignment for functions and labels with -mtuneXi Ruoyao4-0/+27
2023-06-15middle-end, i386: Pattern recognize add/subtract with carry [PR79173]Jakub Jelinek1-4/+69
2023-06-15i386: Add peephole2 patterns to improve subtract with borrow with memory dest...Jakub Jelinek1-3/+151
2023-06-15i386: Add peephole2 patterns to improve add with carry or subtract with borro...Jakub Jelinek1-0/+289
2023-06-15AArch64: New RTL for ABDOluwatamilore Adebayo2-2/+14
2023-06-15LoongArch: Change the default value of LARCH_CALL_RATIO to 6.chenxiaolong1-1/+1
2023-06-15RISC-V: Use merge approach to optimize vector permutationJuzhe-Zhong1-0/+53
2023-06-15RISC-V: Ensure vector args and return use function stack to pass [PR110119]Lehua Ding1-5/+12
2023-06-15RISC-V: Align the predictor style for define_insn_and_splitPan Li2-22/+22
2023-06-15RISC-V: Bugfix for vec_init repeating auto vectorization in RV32Pan Li1-4/+12
2023-06-14Remove MFWRAP_SPEC remnantJivan Hakobyan1-8/+0
2023-06-14aarch64: Fix -Werror=sign-compare bootstrap failureKyrylo Tkachov1-3/+3
2023-06-14driver: Forward '-lgfortran', '-lm' to offloading compilationThomas Schwinge2-0/+24
2023-06-14Use x instead of v for alternative 2 (v, BH) in mov<mode>_internal.liuhongt1-1/+1
2023-06-13Remove sh5media divtab codeJeff Law1-203/+0
2023-06-13i386: Fix up whitespace in assemblyJakub Jelinek1-3/+3
2023-06-13RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`Lehua Ding1-1/+2
2023-06-13RISC-V: Add comments of some functionsJuzhe-Zhong1-0/+7
2023-06-13RISC-V: Fix bug of VLA SLP auto-vectorizationJuzhe-Zhong1-4/+4
2023-06-13RISC-V: Add vector psabi checking.Yanzhang Wang3-2/+117
2023-06-13arm: Extend -mtp= argumentsKyrylo Tkachov6-6/+48
2023-06-13aarch64: Extend -mtp= argumentsKyrylo Tkachov3-2/+19
2023-06-13AArch64: [PR96339] Optimise svlast[ab]Tejas Belagod1-0/+133
2023-06-12Update perf auto profile scriptAndi Kleen1-1/+8
2023-06-13RISC-V: Fix V_WHOLE && V_FRACT iterator requirementJuzhe-Zhong1-7/+10
2023-06-13RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operationJuzhe-Zhong1-0/+111
2023-06-12[aarch64] Improve code-gen for vector initialization with single constant ele...Prathamesh Kulkarni1-8/+30
2023-06-12RISC-V: Support RVV FP16 MISC vget/vset intrinsic APIPan Li1-0/+3
2023-06-12RISC-V: Add RVV narrow shift right lowering auto-vectorizationJuzhe-Zhong2-14/+75
2023-06-12Add missing vec_pack/unpacks patterns for _Float16 <-> int/float conversion.liuhongt1-9/+207
2023-06-12rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]Kewen Lin1-7/+7
2023-06-12rs6000: Don't use TFmode for 128 bits fp constant in toc [PR110011]Kewen Lin1-1/+1
2023-06-12RISC-V: Support RVV FP16 MISC vlmul ext intrinsic APIPan Li1-0/+15
2023-06-11aix: Debugging does not require a stack frame.David Edelsohn1-3/+0
2023-06-11Use canonical form for reversed single-bit insertions after reload.Georg-Johann Lay3-111/+41
2023-06-11target/19907: Overhaul bit extractions.Georg-Johann Lay5-114/+519
2023-06-11RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASSJuzhe-Zhong2-150/+288
2023-06-10target/109650: Fix wrong code after cc0 -> CCmode transition.Georg-Johann Lay7-777/+1318
2023-06-10RISC-V: Enable select_vl for RVV auto-vectorizationJuzhe-Zhong3-0/+27
2023-06-09RISC-V: Refactor requirement of ZVFH and ZVFHMIN.Pan Li2-16/+46
2023-06-09RISC-V: Fix one warning of frm enum.Pan Li1-7/+10
2023-06-09Explicitly view_convert_expr mask to signed type when folding pblendvb builtins.liuhongt1-1/+3
2023-06-09Fold _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple ABSU_EXPR + VCE.liuhongt2-10/+23
2023-06-08i386: Fix endless recursion in ix86_expand_vector_init_general with MMX [PR11...Jakub Jelinek1-1/+1
2023-06-07Add support for stc and cmc instructions in i386.mdRoger Sayle5-4/+126
2023-06-07RISC-V: Eliminate extension after for *w instructionsJeff Law4-31/+177
2023-06-07riscv: Fix scope for memory model calculationDimitar Dimitrov1-4/+9
2023-06-07riscv: Fix insn cost calculationDimitar Dimitrov1-1/+1
2023-06-07aarch64: Allow compiler to define ls64 builtins [PR110132]Alex Coplan2-38/+19
2023-06-07aarch64: Fix wrong code with st64b builtin [PR110100]Alex Coplan2-2/+2