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| author | Alex Coplan <alex.coplan@arm.com> | 2023-06-06 11:52:19 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2023-06-07 17:42:42 +0100 |
| commit | 737a0b749a7bc3e7cb904ea2d4b18dc130514b85 (patch) | |
| tree | ad30eadab698e4cc41f354daf8d414640139b943 /gcc/config | |
| parent | 713613541254039a34e1dd8fd4a613a299af1fd6 (diff) | |
| download | gcc-737a0b749a7bc3e7cb904ea2d4b18dc130514b85.zip gcc-737a0b749a7bc3e7cb904ea2d4b18dc130514b85.tar.gz gcc-737a0b749a7bc3e7cb904ea2d4b18dc130514b85.tar.bz2 | |
aarch64: Fix wrong code with st64b builtin [PR110100]
The st64b pattern incorrectly had an output constraint on the register
operand containing the destination address for the store, leading to
wrong code. This patch fixes that.
gcc/ChangeLog:
PR target/110100
* config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64):
Use input operand for the destination address.
* config/aarch64/aarch64.md (st64b): Fix constraint on address
operand.
gcc/testsuite/ChangeLog:
PR target/110100
* gcc.target/aarch64/acle/pr110100.c: New test.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-builtins.cc | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index d4810913..1a4507f 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -2519,7 +2519,7 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) { rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], op0, DImode); + create_input_operand (&ops[0], op0, DImode); create_input_operand (&ops[1], op1, V8DImode); expand_insn (CODE_FOR_st64b, 2, ops); return const0_rtx; diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 11d0d9c..ac39a4d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -7928,7 +7928,7 @@ ) (define_insn "st64b" - [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r")) + [(set (mem:V8DI (match_operand:DI 0 "register_operand" "r")) (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] UNSPEC_ST64B) )] |