RISC-V: Add RVV narrow shift right lowering auto-vectorization

Optimize the following auto-vectorization codes:
void foo (int16_t * __restrict a, int32_t * __restrict b, int32_t c, int n)
{
    for (int i = 0; i < n; i++)
      a[i] = b[i] >> c;
}

Before this patch:
foo:
        ble     a3,zero,.L5
.L3:
        vsetvli a5,a3,e32,m1,ta,ma
        vle32.v v1,0(a1)
        vsetvli a4,zero,e32,m1,ta,ma
        vsra.vx v1,v1,a2
        vsetvli zero,zero,e16,mf2,ta,ma
        slli    a7,a5,2
        vncvt.x.x.w     v1,v1
        slli    a6,a5,1
        vsetvli zero,a5,e16,mf2,ta,ma
        sub     a3,a3,a5
        vse16.v v1,0(a0)
        add     a1,a1,a7
        add     a0,a0,a6
        bne     a3,zero,.L3
.L5:
        ret

After this patch:
foo:
	ble	a3,zero,.L5
.L3:
	vsetvli	a5,a3,e32,m1,ta,ma
	vle32.v	v1,0(a1)
	vsetvli	a7,zero,e16,mf2,ta,ma
	slli	a6,a5,2
	vnsra.wx	v1,v1,a2
	slli	a4,a5,1
	vsetvli	zero,a5,e16,mf2,ta,ma
	sub	a3,a3,a5
	vse16.v	v1,0(a0)
	add	a1,a1,a6
	add	a0,a0,a4
	bne	a3,zero,.L3
.L5:
	ret

gcc/ChangeLog:

	* config/riscv/autovec-opt.md
	(*v<any_shiftrt:optab><any_extend:optab>trunc<mode>): New pattern.
	(*<any_shiftrt:optab>trunc<mode>): Ditto.
	* config/riscv/autovec.md (<optab><mode>3): Change to
	define_insn_and_split.
	(v<optab><mode>3): Ditto.
	(trunc<mode><v_double_trunc>2): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/narrow-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/narrow-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/narrow-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: New test.

2 files changed, 75 insertions, 14 deletions

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 7bb93ee..aef28e4 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -330,3 +330,49 @@
   }
   [(set_attr "type" "viwmuladd")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Binary narrow shifts.
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vnsrl.wv/vnsrl.wx/vnsrl.wi
+;; - vnsra.wv/vnsra.wx/vnsra.wi
+;; -------------------------------------------------------------------------
+
+(define_insn_and_split "*v<any_shiftrt:optab><any_extend:optab>trunc<mode>"
+  [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand"       "=vr,vr")
+    (truncate:<V_DOUBLE_TRUNC>
+      (any_shiftrt:VWEXTI
+        (match_operand:VWEXTI 1 "register_operand"                 " vr,vr")
+	(any_extend:VWEXTI
+          (match_operand:<V_DOUBLE_TRUNC> 2 "vector_shift_operand" " vr,vk")))))]
+  "TARGET_VECTOR"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
+{
+  insn_code icode = code_for_pred_narrow (<any_shiftrt:CODE>, <MODE>mode);
+  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands);
+  DONE;
+}
+ [(set_attr "type" "vnshift")
+  (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+(define_insn_and_split "*<any_shiftrt:optab>trunc<mode>"
+  [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr")
+    (truncate:<V_DOUBLE_TRUNC>
+      (any_shiftrt:VWEXTI
+        (match_operand:VWEXTI 1 "register_operand"           " vr")
+	(match_operand:<VEL> 2 "csr_operand"                 " rK"))))]
+  "TARGET_VECTOR"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
+{
+  operands[2] = gen_lowpart (Pmode, operands[2]);
+  insn_code icode = code_for_pred_narrow_scalar (<any_shiftrt:CODE>, <MODE>mode);
+  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands);
+  DONE;
+}
+ [(set_attr "type" "vnshift")
+  (set_attr "mode" "<V_DOUBLE_TRUNC>")])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b707009..eadc2c5 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -150,18 +150,23 @@
 ;; - vsll.vi/vsra.vi/vsrl.vi
 ;; -------------------------------------------------------------------------
 
-(define_expand "<optab><mode>3"
-  [(set (match_operand:VI 0 "register_operand")
+(define_insn_and_split "<optab><mode>3"
+  [(set (match_operand:VI 0 "register_operand" "=vr")
     (any_shift:VI
-     (match_operand:VI 1 "register_operand")
-     (match_operand:<VEL> 2 "csr_operand")))]
+     (match_operand:VI 1 "register_operand"    " vr")
+     (match_operand:<VEL> 2 "csr_operand"      " rK")))]
   "TARGET_VECTOR"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
 {
   operands[2] = gen_lowpart (Pmode, operands[2]);
   riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<CODE>, <MODE>mode),
 				 riscv_vector::RVV_BINOP, operands);
   DONE;
-})
+}  
+ [(set_attr "type" "vshift")
+  (set_attr "mode" "<MODE>")])
 
 ;; -------------------------------------------------------------------------
 ;; ---- [INT] Binary shifts by scalar.
@@ -170,17 +175,22 @@
 ;; - vsll.vv/vsra.vv/vsrl.vv
 ;; -------------------------------------------------------------------------
 
-(define_expand "v<optab><mode>3"
-  [(set (match_operand:VI 0 "register_operand")
+(define_insn_and_split "v<optab><mode>3"
+  [(set (match_operand:VI 0 "register_operand"  "=vr,vr")
     (any_shift:VI
-     (match_operand:VI 1 "register_operand")
-     (match_operand:VI 2 "vector_shift_operand")))]
+     (match_operand:VI 1 "register_operand"     " vr,vr")
+     (match_operand:VI 2 "vector_shift_operand" " vr,vk")))]
   "TARGET_VECTOR"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
 {
   riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
 				 riscv_vector::RVV_BINOP, operands);
   DONE;
-})
+}
+ [(set_attr "type" "vshift")
+  (set_attr "mode" "<MODE>")])
 
 ;; -------------------------------------------------------------------------
 ;; ---- [BOOL] Binary logical operations
@@ -395,16 +405,21 @@
 ;; -------------------------------------------------------------------------
 ;; - vncvt.x.x.w
 ;; -------------------------------------------------------------------------
-(define_expand "trunc<mode><v_double_trunc>2"
-  [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
+(define_insn_and_split "trunc<mode><v_double_trunc>2"
+  [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr")
     (truncate:<V_DOUBLE_TRUNC>
-     (match_operand:VWEXTI 1 "register_operand")))]
+     (match_operand:VWEXTI 1 "register_operand"              " vr")))]
   "TARGET_VECTOR"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
 {
   insn_code icode = code_for_pred_trunc (<MODE>mode);
   riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
   DONE;
-})
+}
+  [(set_attr "type" "vshift")
+   (set_attr "mode" "<MODE>")])
 
 ;; -------------------------------------------------------------------------
 ;; Truncation to a mode whose inner mode size is a quarter of mode's.