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2017-01-06[ARM] Implement support for ACLE Coprocessor LDC and STC intrinsicsAndre Vieira9-0/+210
2017-01-06[ARM] Implement support for ACLE Coprocessor CDP intrinsicsAndre Vieira11-24/+131
2017-01-06[ARM] Move CRC builtins to refactored frameworkAndre Vieira2-69/+110
2017-01-06[ARM] Refactor NEON builtin framework to work for other builtinsAndre Vieira1-57/+72
2017-01-05Introduce RTL function readerDavid Malcolm2-0/+263
2017-01-05i386.md (*testqi_ext_3): No need to handle memory operands in a special way.Uros Bizjak1-21/+15
2017-01-05S/390: Unroll mvc loop for memcpy with small constant lengths.Andreas Krebbel1-3/+18
2017-01-05S/390: Unroll mvc/xc loop for memset with small constantAndreas Krebbel1-22/+34
2017-01-05S/390: memset: Avoid overlapping MVC operands between iterations.Andreas Krebbel1-31/+64
2017-01-05re PR target/71977 (powerpc64: Use VSR when operating on float and integer)Michael Meissner6-35/+578
2017-01-04re PR target/78056 (build failure on Power7)Kelvin Nilsen1-1/+80
2017-01-04i386.md (HI/SImode test with imm to QImode splitters): Use gen_int_mode inste...Uros Bizjak2-7/+7
2017-01-04re PR target/78900 (ICE in gcc.target/powerpc/signbit-3.c)Michael Meissner3-18/+33
2017-01-03invoke.texi (SPARC options): Document -mlra as the default.Eric Botcazou1-0/+4
2017-01-02darwin-driver.c (darwin_driver_init): Const-correctness fixes for first_perio...Jeff Law1-2/+2
2017-01-02re PR target/78967 (inserts are not effective)Uros Bizjak1-7/+63
2017-01-01Update copyright years.Jakub Jelinek1345-1359/+1359
2016-12-30i386.md (*testqi_ext_3): Merge insn pattern and corresponding splitter to def...Uros Bizjak1-34/+22
2016-12-30predicates.md (ext_register_operand): Do not reject registers without upper p...Uros Bizjak2-19/+21
2016-12-30* config/i386/i386.md (divmodqi4): Use lowpart_subreg.Uros Bizjak1-3/+2
2016-12-29re PR target/78904 (zero-extracts are not effective)Uros Bizjak1-28/+2
2016-12-29rs6000.c (altivec_expand_builtin): Fix typos in error messages.Michael Meissner1-2/+2
2016-12-28re PR target/78904 (zero-extracts are not effective)Uros Bizjak3-1/+36
2016-12-27predicates.md (const_0_to_12_operand): Rename predicate and change test from ...Michael Meissner4-14/+14
2016-12-27i386.c (ix86_secondary_reload): Require QImode intermediate for QImode mask r...Uros Bizjak1-13/+8
2016-12-27i386.md (VI_512): Remove.Uros Bizjak1-14/+8
2016-12-27re PR translation/78922 (Comment submitted for translation in stringop.opt)Jakub Jelinek1-31/+0
2016-12-27re PR target/78904 (zero-extracts are not effective)Uros Bizjak2-11/+17
2016-12-27i386.md (andqi_ext_1): Use general_operand predicate for operand 2.Uros Bizjak1-11/+12
2016-12-27re PR target/78904 (zero-extracts are not effective)Uros Bizjak2-22/+10
2016-12-26re PR target/78904 (zero-extracts are not effective)Uros Bizjak2-246/+212
2016-12-22Run tests only if the machine supports the instruction set.Dominik Vogt1-0/+17
2016-12-21re PR rtl-optimization/11488 (Pre-regalloc scheduling severely worsens perfor...Pat Haugen1-0/+35
2016-12-21[PATCH, v2, rs6000] pr65479 Add -fasynchronous-unwind-tables when the -fsanit...Bill Seurer1-0/+7
2016-12-21re PR target/71321 (x86: worse code for uint8_t % 10 and / 10)Bernd Schmidt2-0/+55
2016-12-21nvptx: do not assume that crtl->is_leaf is unsetAlexander Monakov1-3/+4
2016-12-20[ARM] PR target/78694: Avoid invalid RTL sharing in minipool codeKyrylo Tkachov1-5/+7
2016-12-19rs6000-protos.h (expand_strn_compare): Declare.Aaron Sawdey4-4/+417
2016-12-19i386.md (*popcounthi2_1): New insn_and_split pattern.Uros Bizjak1-0/+18
2016-12-19rs6000.c: Add handling for early expansion of vector multiply builtins.Will Schmidt1-0/+30
2016-12-19rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of ve...Will Schmidt1-0/+18
2016-12-19PR target/78748: S/390: Fix ICE with ANDC splitter.Dominik Vogt1-1/+5
2016-12-19netbsd.h (LINK_EH_SPEC): Define.Krister Walfridsson1-0/+4
2016-12-17avx512bwintrin.h: Add new k-mask intrinsics.Andrew Senkevich5-3/+47
2016-12-17i386.md (*tzcnt<mode>_1): Merge *tzcnt<mode>_1_falsedep_1 and *tzcnt<mode>_1 ...Uros Bizjak1-147/+106
2016-12-17byte-in-either-range-0.c: New test.Kelvin Nilsen3-0/+229
2016-12-16[AArch64] Split X-reg UBFIZ into W-reg LSL when possibleKyrylo Tkachov1-0/+18
2016-12-16[AArch64] Split X-reg UBFX into W-reg LSR when possibleKyrylo Tkachov1-0/+20
2016-12-16The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 doesn'...Wilco Dijkstra2-36/+12
2016-12-16Thumb uses a special register allocation order to increase the use of low reg...Wilco Dijkstra1-1/+1
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