predicates.md (const_0_to_12_operand): Rename predicate and change test from 0..11 to 0..12 to match the semantics of...

[gcc]
2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (const_0_to_12_operand): Rename
	predicate and change test from 0..11 to 0..12 to match the
	semantics of the word extract/insert instructions.  Change all
	callers.
	(const_0_to_11_operand): Likewise.
	* config/rs6000/rs6000.c (altivec_expand_builtin): Likewise.
	* config/rs6000/vsx.md (vextract4b): Likewise.
	(vextract4b_internal): Likewise.
	(vinsert4b): Likewise.
	(vinsert4b_internal): Likewise.
	(vinsert4b_di): Likewise.
	(vinsert4b_di_internal): Likewise.
	* config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used
	in xxextractuw to zero extend the word in the vector registers.
	(lfiwzx): Likewise.

[gcc/testsuite]
2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13
	being out of bounds instead of 12.

From-SVN: r243948

4 files changed, 14 insertions, 14 deletions

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 30b2123..8caf710 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -211,9 +211,9 @@
        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 
 ;; Match op = 0..11
-(define_predicate "const_0_to_11_operand"
+(define_predicate "const_0_to_12_operand"
   (and (match_code "const_int")
-       (match_test "IN_RANGE (INTVAL (op), 0, 11)")))
+       (match_test "IN_RANGE (INTVAL (op), 0, 12)")))
 
 ;; Match op = 0..15
 (define_predicate "const_0_to_15_operand"
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 77bb548..e100a01 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15839,9 +15839,9 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
       if (arg1 == error_mark_node)
 	return expand_call (exp, target, false);
 
-      if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 11)
+      if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
 	{
-	  error ("second argument to vec_vextract4b must 0..11");
+	  error ("second argument to vec_vextract4b must 0..12");
 	  return expand_call (exp, target, false);
 	}
       break;
@@ -15856,9 +15856,9 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
       if (arg2 == error_mark_node)
 	return expand_call (exp, target, false);
 
-      if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 11)
+      if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
 	{
-	  error ("third argument to vec_vinsert4b must 0..11");
+	  error ("third argument to vec_vinsert4b must 0..12");
 	  return expand_call (exp, target, false);
 	}
       break;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index abd2ce8..b9f75f9 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -855,7 +855,7 @@
    lxsiwzx %x0,%y1
    mtvsrwz %x0,%1
    mfvsrwz %0,%x1
-   xxextractuw %x0,%x1,1"
+   xxextractuw %x0,%x1,4"
   [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")])
 
 (define_insn_and_split "*zero_extendsi<mode>2_dot"
@@ -5131,7 +5131,7 @@
    lfiwzx %0,%y1
    lxsiwzx %x0,%y1
    mtvsrwz %x0,%1
-   xxextractuw %x0,%x1,1"
+   xxextractuw %x0,%x1,4"
   [(set_attr "type" "fpload,fpload,mftgpr,vecexts")])
 
 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7aecbe6..0b1a5a3 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3813,7 +3813,7 @@
 (define_expand "vextract4b"
   [(set (match_operand:DI 0 "gpc_reg_operand")
 	(unspec:DI [(match_operand:V16QI 1 "vsx_register_operand")
-		    (match_operand:QI 2 "const_0_to_11_operand")]
+		    (match_operand:QI 2 "const_0_to_12_operand")]
 		   UNSPEC_XXEXTRACTUW))]
   "TARGET_P9_VECTOR"
 {
@@ -3824,7 +3824,7 @@
 (define_insn_and_split "*vextract4b_internal"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=wj,r")
 	(unspec:DI [(match_operand:V16QI 1 "vsx_register_operand" "wa,v")
-		    (match_operand:QI 2 "const_0_to_11_operand" "n,n")]
+		    (match_operand:QI 2 "const_0_to_12_operand" "n,n")]
 		   UNSPEC_XXEXTRACTUW))]
   "TARGET_P9_VECTOR"
   "@
@@ -3852,7 +3852,7 @@
   [(set (match_operand:V16QI 0 "vsx_register_operand")
 	(unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand")
 		       (match_operand:V16QI 2 "vsx_register_operand")
-		       (match_operand:QI 3 "const_0_to_11_operand")]
+		       (match_operand:QI 3 "const_0_to_12_operand")]
 		   UNSPEC_XXINSERTW))]
   "TARGET_P9_VECTOR"
 {
@@ -3870,7 +3870,7 @@
   [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
 	(unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand" "wa")
 		       (match_operand:V16QI 2 "vsx_register_operand" "0")
-		       (match_operand:QI 3 "const_0_to_11_operand" "n")]
+		       (match_operand:QI 3 "const_0_to_12_operand" "n")]
 		   UNSPEC_XXINSERTW))]
   "TARGET_P9_VECTOR"
   "xxinsertw %x0,%x1,%3"
@@ -3880,7 +3880,7 @@
   [(set (match_operand:V16QI 0 "vsx_register_operand")
 	(unspec:V16QI [(match_operand:DI 1 "vsx_register_operand")
 		       (match_operand:V16QI 2 "vsx_register_operand")
-		       (match_operand:QI 3 "const_0_to_11_operand")]
+		       (match_operand:QI 3 "const_0_to_12_operand")]
 		   UNSPEC_XXINSERTW))]
   "TARGET_P9_VECTOR"
 {
@@ -3892,7 +3892,7 @@
   [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
 	(unspec:V16QI [(match_operand:DI 1 "vsx_register_operand" "wj")
 		       (match_operand:V16QI 2 "vsx_register_operand" "0")
-		       (match_operand:QI 3 "const_0_to_11_operand" "n")]
+		       (match_operand:QI 3 "const_0_to_12_operand" "n")]
 		   UNSPEC_XXINSERTW))]
   "TARGET_P9_VECTOR"
   "xxinsertw %x0,%x1,%3"