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| author | Uros Bizjak <ubizjak@gmail.com> | 2017-01-02 23:08:18 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2017-01-02 23:08:18 +0100 |
| commit | 8b7163c6300bac42bebc71e331d4e750d5a35f12 (patch) | |
| tree | 8253019db859fde2bfa051e3694d4b04ed5fd321 /gcc/config | |
| parent | 11627b814e47520596a11e7c37378e4b0055f2d3 (diff) | |
| download | gcc-8b7163c6300bac42bebc71e331d4e750d5a35f12.zip gcc-8b7163c6300bac42bebc71e331d4e750d5a35f12.tar.gz gcc-8b7163c6300bac42bebc71e331d4e750d5a35f12.tar.bz2 | |
re PR target/78967 (inserts are not effective)
target/78967
* config/i386/i386.md (UNSPEC_NOREX_MEM): New unspec.
(*insvqi_1): New insn pattern.
(*insvqi_1_mem_rex64): Ditto.
(*insvqi_2): Ditto.
(*insvqi_3): Rename from *insvqi.
(*extzvqi_mem_rex64): Add UNSPEC_NOREX_MEM tag.
testsuite/ChangeLog:
PR target/78967
* gcc.target/i386/pr78967-1.c: New test.
* gcc.target/i386/pr78967-2.c: Ditto.
* gcc.target/i386/pr78967-3.c: Ditto.
* gcc.target/i386/pr78904-2.c: Tighten scan-asm patterns.
* gcc.target/i386/pr78904-4.c: Ditto.
* gcc.target/i386/pr78904-6.c: Ditto.
From-SVN: r244006
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 70 |
1 files changed, 63 insertions, 7 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 511d3a7..c947955 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -114,6 +114,7 @@ UNSPEC_STOS UNSPEC_PEEPSIB UNSPEC_INSN_FALSE_DEP + UNSPEC_NOREX_MEM ;; For SSE/MMX support: UNSPEC_FIX_NOTRUNC @@ -2819,7 +2820,8 @@ (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) - (const_int 8)) 0))] + (const_int 8)) 0)) + (unspec [(const_int 0)] UNSPEC_NOREX_MEM)] "TARGET_64BIT && reload_completed" "mov{b}\t{%h1, %0|%0, %h1}" [(set_attr "type" "imov") @@ -2862,11 +2864,13 @@ (set (match_operand:QI 2 "norex_memory_operand") (match_dup 0))] "TARGET_64BIT && peep2_reg_dead_p (2, operands[0])" - [(set (match_dup 2) - (subreg:QI - (zero_extract:SI (match_dup 1) - (const_int 8) - (const_int 8)) 0))]) + [(parallel + [(set (match_dup 2) + (subreg:QI + (zero_extract:SI (match_dup 1) + (const_int 8) + (const_int 8)) 0)) + (unspec [(const_int 0)] UNSPEC_NOREX_MEM)])]) (define_expand "insv<mode>" [(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand") @@ -2916,7 +2920,59 @@ (set_attr "type" "imov") (set_attr "mode" "QI")]) -(define_insn "*insvqi" +(define_insn "*insvqi_1_mem_rex64" + [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") + (const_int 8) + (const_int 8)) + (subreg:SI + (match_operand:QI 1 "norex_memory_operand" "Bn") 0)) + (unspec [(const_int 0)] UNSPEC_NOREX_MEM)] + "TARGET_64BIT && reload_completed" + "mov{b}\t{%1, %h0|%h0, %1}" + [(set_attr "type" "imov") + (set_attr "mode" "QI")]) + +(define_insn "*insvqi_1" + [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q,Q") + (const_int 8) + (const_int 8)) + (subreg:SI + (match_operand:QI 1 "general_operand" "QnBc,m") 0))] + "" + "mov{b}\t{%1, %h0|%h0, %1}" + [(set_attr "isa" "*,nox64") + (set_attr "type" "imov") + (set_attr "mode" "QI")]) + +(define_peephole2 + [(set (match_operand:QI 0 "register_operand") + (match_operand:QI 1 "norex_memory_operand")) + (set (zero_extract:SI (match_operand 2 "ext_register_operand") + (const_int 8) + (const_int 8)) + (subreg:SI (match_dup 0) 0))] + "TARGET_64BIT + && peep2_reg_dead_p (2, operands[0])" + [(parallel + [(set (zero_extract:SI (match_dup 2) + (const_int 8) + (const_int 8)) + (subreg:SI (match_dup 1) 0)) + (unspec [(const_int 0)] UNSPEC_NOREX_MEM)])]) + +(define_insn "*insvqi_2" + [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") + (const_int 8) + (const_int 8)) + (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") + (const_int 8) + (const_int 8)))] + "" + "mov{b}\t{%h1, %h0|%h0, %h1}" + [(set_attr "type" "imov") + (set_attr "mode" "QI")]) + +(define_insn "*insvqi_3" [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") (const_int 8) (const_int 8)) |