riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-13	AArch64: [PR96339] Optimise svlast[ab]	Tejas Belagod	1	-0/+133
2023-06-12	Update perf auto profile script	Andi Kleen	1	-1/+8
2023-06-13	RISC-V: Fix V_WHOLE && V_FRACT iterator requirement	Juzhe-Zhong	1	-7/+10
2023-06-13	RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation	Juzhe-Zhong	1	-0/+111
2023-06-12	[aarch64] Improve code-gen for vector initialization with single constant ele...	Prathamesh Kulkarni	1	-8/+30
2023-06-12	RISC-V: Support RVV FP16 MISC vget/vset intrinsic API	Pan Li	1	-0/+3
2023-06-12	RISC-V: Add RVV narrow shift right lowering auto-vectorization	Juzhe-Zhong	2	-14/+75
2023-06-12	Add missing vec_pack/unpacks patterns for _Float16 <-> int/float conversion.	liuhongt	1	-9/+207
2023-06-12	rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]	Kewen Lin	1	-7/+7
2023-06-12	rs6000: Don't use TFmode for 128 bits fp constant in toc [PR110011]	Kewen Lin	1	-1/+1
2023-06-12	RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API	Pan Li	1	-0/+15
2023-06-11	aix: Debugging does not require a stack frame.	David Edelsohn	1	-3/+0
2023-06-11	Use canonical form for reversed single-bit insertions after reload.	Georg-Johann Lay	3	-111/+41
2023-06-11	target/19907: Overhaul bit extractions.	Georg-Johann Lay	5	-114/+519
2023-06-11	RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS	Juzhe-Zhong	2	-150/+288
2023-06-10	target/109650: Fix wrong code after cc0 -> CCmode transition.	Georg-Johann Lay	7	-777/+1318
2023-06-10	RISC-V: Enable select_vl for RVV auto-vectorization	Juzhe-Zhong	3	-0/+27
2023-06-09	RISC-V: Refactor requirement of ZVFH and ZVFHMIN.	Pan Li	2	-16/+46
2023-06-09	RISC-V: Fix one warning of frm enum.	Pan Li	1	-7/+10
2023-06-09	Explicitly view_convert_expr mask to signed type when folding pblendvb builtins.	liuhongt	1	-1/+3
2023-06-09	Fold _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple ABSU_EXPR + VCE.	liuhongt	2	-10/+23
2023-06-08	i386: Fix endless recursion in ix86_expand_vector_init_general with MMX [PR11...	Jakub Jelinek	1	-1/+1
2023-06-07	Add support for stc and cmc instructions in i386.md	Roger Sayle	5	-4/+126
2023-06-07	RISC-V: Eliminate extension after for *w instructions	Jeff Law	4	-31/+177
2023-06-07	riscv: Fix scope for memory model calculation	Dimitar Dimitrov	1	-4/+9
2023-06-07	riscv: Fix insn cost calculation	Dimitar Dimitrov	1	-1/+1
2023-06-07	aarch64: Allow compiler to define ls64 builtins [PR110132]	Alex Coplan	2	-38/+19
2023-06-07	aarch64: Fix wrong code with st64b builtin [PR110100]	Alex Coplan	2	-2/+2
2023-06-07	aarch64: Fix whitespace in ls64 builtin implementation [PR110100]	Alex Coplan	2	-43/+43
2023-06-07	aarch64: Represent SQXTUN with RTL operations	Kyrylo Tkachov	3	-14/+56
2023-06-07	aarch64: Improve RTL representation of ADDP instructions	Kyrylo Tkachov	1	-7/+63
2023-06-07	RISC-V: Support RVV VLA SLP auto-vectorization	Juzhe-Zhong	3	-23/+394
2023-06-07	RISC-V: Fix ICE when include riscv_vector.h with rv64gcv	Pan Li	1	-33/+33
2023-06-06	RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization	Juzhe-Zhong	2	-0/+161
2023-06-06	rs6000: genfusion: Delete dead code	Segher Boessenkool	1	-3/+0
2023-06-06	rs6000: genfusion: Rewrite load/compare code	Segher Boessenkool	1	-82/+103
2023-06-06	rs6000: Remove duplicate expression [PR106907]	Jeevitha Palanisamy	1	-1/+0
2023-06-06	aarch64: Improve representation of vpaddd intrinsics	Kyrylo Tkachov	4	-14/+3
2023-06-06	aarch64: Reimplement URSHR,SRSHR patterns with standard RTL codes	Kyrylo Tkachov	1	-7/+37
2023-06-06	aarch64: Simplify SHRN, RSHRN expanders and patterns	Kyrylo Tkachov	1	-80/+11
2023-06-06	aarch64: Improve representation of ADDLV instructions	Kyrylo Tkachov	5	-11/+125
2023-06-06	RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API	Pan Li	2	-0/+19
2023-06-05	[RISC-V] correct machine mode in save-restore cfi RTL.	Fei Gao	1	-5/+5
2023-06-06	RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.	Li Xu	2	-16/+16
2023-06-06	RISC-V: Fix some typo in vector-iterators.md	Pan Li	1	-4/+4
2023-06-05	internal-fn,vect: Refactor widen_plus as internal_fn	Andre Vieira	1	-4/+4
2023-06-05	RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API	Pan Li	2	-0/+53
2023-06-05	MIPS: Add speculation_barrier support	YunQiang Su	3	-0/+26
2023-06-05	RISC-V: Reorganize riscv-v.cc	Juzhe-Zhong	1	-248/+249
2023-06-05	RISC-V: Split arguments of expand_vec_perm	Juzhe-Zhong	3	-7/+4