riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-05-18	RISC-V: Add RV32E support.	Kito Cheng	5	-8/+44
2018-05-17	RISC-V: Optimize switch with sign-extended index.	Jim Wilson	1	-2/+12
2018-05-16	RISC-V: Minor pattern name cleanup.	Jim Wilson	1	-4/+4
2018-05-09	RISC-V: Add with-multilib-list support.	Jim Wilson	2	-0/+57
2018-05-08	[PATCH] RISC-V: Use new linker emulations for glibc ABI.	Jim Wilson	1	-2/+10
2018-04-20	RISC-V: Pass --no-relax to linker if -mno-relax is present.	Kito Cheng	2	-0/+2
2018-04-20	RISC-V: Make sure stack is always aligned during adjusting stack.	Kito Cheng	1	-1/+2
2018-04-17	RISC-V: Fix 32-bit stack pointer alignment problem.	Jim Wilson	1	-3/+5
2018-04-06	RISC-V: Support for FreeBSD.	Ruslan Bukin	1	-0/+54
2018-04-02	RISC-V: Fix for combine bug with shift and AND operations.	Jim Wilson	3	-7/+138
2018-03-19	RISC-V: Fix bootstrap failure.	Jim Wilson	2	-8/+8
2018-03-13	RISC-V: Add and document the "-mno-relax" option	Palmer Dabbelt	2	-0/+10
2018-02-14	RISC-V: Change sp subtracts so prologue stores can compress.	Jim Wilson	2	-6/+28
2018-02-13	RISC-V: define _REENTRANT with -pthread	Andreas Schwab	1	-0/+2
2018-01-26	RISC-V: Allow register pairs for 64-bit target.	Jim Wilson	1	-0/+4
2018-01-26	RISC-V: Add --specs=nosys.specs support.	Jim Wilson	1	-1/+1
2018-01-23	RISC-V: Add -mpreferred-stack-boundary option.	Andrew Waterman	3	-5/+33
2018-01-17	RISC-V: Mark fsX as call clobbered when soft-float.	Andrew Waterman	1	-0/+7
2018-01-15	RISC-V: Increase mult/div cost if not implemented in hardware.	Andrew Waterman	1	-1/+7
2018-01-10	RISC-V: Add naked function support.	Kito Cheng	3	-18/+144
2018-01-08	RISC-V: Fix -msave-restore bug with sibcalls.	Jim Wilson	1	-16/+2
2018-01-03	Update copyright years.	Jakub Jelinek	20	-20/+20
2018-01-02	RISC-V: Fix for icache flush issue on multicore processors.	Andrew Waterman	2	-0/+8
2017-12-16	poly_int: IN_TARGET_CODE	Richard Sandiford	3	-0/+6
2017-12-07	Add srodata section support to riscv port.	Andrew Waterman	1	-0/+22
2017-12-04	Fix typos in riscv register save/restore.	Jim Wilson	2	-4/+4
2017-11-29	Riscv patterns to optimize away some redundant zero/sign extends.	Jim Wilson	2	-2/+73
2017-11-12	[riscv] Wrap ASM_OUTPUT_LABELREF in do {} while (0)	Tom de Vries	1	-6/+9
2017-11-08	RISC-V: Fix build error	Kito Cheng	3	-4/+6
2017-11-07	RISC-V: Implement movmemsi	Andrew Waterman	4	-4/+190
2017-11-07	RISC-V: Define MUSL_DYNAMIC_LINKER	Michael Clark	1	-0/+11
2017-11-05	RISC-V: Emit "i" suffix for instructions with immediate operands	Michael Clark	2	-19/+25
2017-11-05	RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune	Andrew Waterman	1	-1/+5
2017-11-05	RISC-V: Set SLOW_BYTE_ACCESS=1	Andrew Waterman	1	-1/+6
2017-11-03	RISC-V: Handle non-legitimate address in riscv_legitimize_move	Kito Cheng	1	-0/+16
2017-10-25	RISC-V: Add Sign/Zero extend patterns for PIC loads	Palmer Dabbelt	2	-2/+12
2017-10-23	Convert STARTING_FRAME_OFFSET to a hook	Richard Sandiford	1	-2/+0
2017-09-25	Turn CONSTANT_ALIGNMENT into a hook	Richard Sandiford	2	-16/+14
2017-09-15	Turn TRULY_NOOP_TRUNCATION into a hook	Richard Sandiford	2	-3/+2
2017-09-15	Turn CANNOT_CHANGE_MODE_CLASS into a hook	Richard Sandiford	2	-3/+11
2017-09-13	Turn SECONDARY_MEMORY_NEEDED into a hook	Richard Sandiford	2	-7/+17
2017-09-12	Turn HARD_REGNO_NREGS into a target hook	Richard Sandiford	3	-15/+14
2017-09-12	Turn SLOW_UNALIGNED_ACCESS into a target hook	Richard Sandiford	2	-6/+14
2017-09-04	Turn MODES_TIEABLE_P into a target hook	Richard Sandiford	2	-7/+16
2017-09-04	Turn HARD_REGNO_MODE_OK into a target hook	Richard Sandiford	3	-8/+6
2017-09-04	PR82045: Avoid passing machine modes through "..."	Richard Sandiford	1	-1/+1
2017-08-08	trans.c: Include header files.	Martin Liska	1	-0/+2
2017-07-27	Add RTEMS support	Sebastian Huber	1	-0/+31
2017-07-12	riscv.c: Remove unnecessary includes.	Jeff Law	2	-58/+3
2017-07-05	Remove enum before machine_mode	Richard Sandiford	2	-56/+56