riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
4 days	[PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register	Yixuan Chen	1	-1/+1
4 days	RISC-V: Add more vector-vector extract cases.	Robin Dapp	2	-0/+212
10 days	[PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern i...	Jin Ma	1	-7/+9
10 days	[PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expre...	Xianmiao Qu	1	-1/+1
10 days	[PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.	Xianmiao Qu	1	-1/+3
10 days	[PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx	Bohan Lei	1	-4/+4
11 days	RISC-V: Implement SAT_ADD for signed integer vector	Pan Li	3	-0/+21
13 days	riscv: Fix duplicate assmbler label in @tlsdesc<mode> insn	Andreas Schwab	2	-11/+8
2024-09-12	RISC-V: Eliminate latter vsetvl when fused	Bohan Lei	1	-0/+3
2024-09-12	RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass	garthlei	1	-5/+11
2024-09-07	[PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model	Zhao Dingyi	1	-3/+8
2024-09-07	[PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e3...	Jin Ma	1	-2/+2
2024-09-05	[PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halves	Raphael Moreira Zinsly	1	-0/+30
2024-09-05	[PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements	Raphael Moreira Zinsly	1	-6/+132
2024-09-05	[V2][RISC-V] Avoid unnecessary extensions after sCC insns	Jeff Law	1	-5/+41
2024-09-04	[PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants	Raphael Moreira Zinsly	1	-8/+21
2024-09-04	RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD	Pan Li	2	-3/+3
2024-09-03	[PR target/115921] Improve reassociation for rv64	Jeff Law	1	-4/+6
2024-09-03	RISC-V: Support form 1 of integer scalar .SAT_ADD	Pan Li	3	-0/+102
2024-09-01	[PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.	Xianmiao Qu	1	-0/+5
2024-09-02	RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64	Pan Li	1	-53/+46
2024-08-29	Use std::unique_ptr for optinfo_item	David Malcolm	2	-0/+2
2024-08-29	RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].	Robin Dapp	3	-0/+248
2024-08-28	RISC-V: Add missing mode_idx for vrol and vror	Kito Cheng	1	-1/+1
2024-08-27	RISC-V: Move helper functions above expand_const_vector	Patrick O'Neill	1	-66/+66
2024-08-27	RISC-V: Allow non-duplicate bool patterns in expand_const_vector	Patrick O'Neill	1	-15/+8
2024-08-27	RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander	Patrick O'Neill	3	-6/+15
2024-08-27	RISC-V: Emit costs for bool and stepped const vectors	Patrick O'Neill	3	-52/+131
2024-08-27	RISC-V: Handle case when constant vector construction target rtx is not a reg...	Patrick O'Neill	1	-32/+41
2024-08-27	RISC-V: Reorder insn cost match order to match corresponding expander match o...	Patrick O'Neill	1	-9/+9
2024-08-27	RISC-V: Fix vid const vector expander for non-npatterns size steps	Patrick O'Neill	1	-6/+42
2024-08-27	RISC-V: Support IMM for operand 1 of ussub pattern	Pan Li	2	-2/+2
2024-08-26	RISC-V: Support IMM for operand 0 of ussub pattern	Pan Li	2	-2/+46
2024-08-25	RISC-V: Fix double mode under RV32 not utilize vf	demin.han	1	-1/+2
2024-08-23	RISC-V: Use encoded nelts when calling repeating_sequence_p	Patrick O'Neill	1	-7/+3
2024-08-23	RISC-V: Expand vec abs without masking.	Robin Dapp	1	-18/+8
2024-08-22	RISC-V: Fix vector cfi notes for stack-clash protection	Raphael Moreira Zinsly	1	-2/+16
2024-08-18	RISC-V: Implement the quad and oct .SAT_TRUNC for scalar	Pan Li	2	-0/+40
2024-08-18	RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]	Pan Li	1	-12/+22
2024-08-17	t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V	Kevin Kirspel	1	-2/+3
2024-08-17	RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics	Jin Ma	1	-40/+40
2024-08-17	[RISC-V][PR target/116282] Stabilize pattern conditions	Jeff Law	4	-31/+55
2024-08-17	RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker	Jin Ma	3	-3/+7
2024-08-17	RISC-V: Bugfix incorrect operand for vwsll auto-vect	Pan Li	1	-0/+4
2024-08-17	RISC-V: Add auto-vect pattern for vector rotate shift	Feng Wang	1	-0/+16
2024-08-17	RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]	曾治金	1	-2/+2
2024-08-15	RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins	Vineet Gupta	1	-0/+63
2024-08-13	RISC-V: Fix non-obvious comment typos	Patrick O'Neill	5	-8/+8
2024-08-09	[RISC-V][PR target/116283] Fix split code for recent Zbs improvements with ma...	Jeff Law	1	-6/+18
2024-08-09	RISC-V: Enable stack clash in alloca	Raphael Moreira Zinsly	2	-0/+34