riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
4 days	RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]	Pan Li	1	-2/+2
5 days	[RISC-V][PR middle-end/118084] Fix brev based reflection code	Jeff Law	1	-6/+15
7 days	RISC-V: Make vector strided store alias all other memories	Pan Li	1	-10/+9
9 days	[PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)	Oliver Kozul	1	-0/+28
9 days	[PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture	Anton Blanchard	2	-0/+30
9 days	RISC-V: Add new constraint R for register even-odd pairs	Kito Cheng	1	-0/+4
9 days	RISC-V: Implment N modifier for printing the register number rather than the ...	Kito Cheng	1	-0/+23
9 days	RISC-V: Rename internal operand modifier N to n	Kito Cheng	3	-5/+5
9 days	RISC-V: Add cr and cf constraint	Kito Cheng	3	-11/+29
9 days	RISC-V: Rename constraint c0* to k0*	Kito Cheng	4	-233/+233
10 days	vect: Do not try to duplicate_and_interleave one-element mode.	Robin Dapp	1	-9/+0
10 days	RISC-V: Fix compress shuffle pattern [PR117383].	Robin Dapp	2	-3/+4
10 days	RISC-V: Increase cost for vec_construct [PR118019].	Robin Dapp	1	-1/+7
13 days	RISC-V: Improve slide1up pattern.	Robin Dapp	3	-15/+56
13 days	RISC-V: Add even/odd vec_perm_const pattern.	Robin Dapp	1	-0/+66
13 days	RISC-V: Add interleave pattern.	Robin Dapp	1	-0/+80
13 days	RISC-V: Add slide to perm_const strategies.	Robin Dapp	1	-0/+99
13 days	RISC-V: Emit vector shift pattern for const_vector [PR117353].	Robin Dapp	1	-3/+5
13 days	RISC-V: Make vector strided load alias all other memories	Pan Li	1	-0/+1
2024-12-09	c++: Allow overloaded builtins to be used in SFINAE context	Matthew Malcomson	1	-2/+2
2024-12-07	Revert "RISC-V: Add const to function_shape::get_name [NFC]"	Kito Cheng	3	-73/+73
2024-12-06	diagnostics: UX: add doc URLs for attributes (v2)	David Malcolm	1	-0/+3
2024-12-06	RISC-V: Add --with-cmodel configure option	Hau Hsu	1	-2/+0
2024-12-05	RISC-V: Add const to function_shape::get_name [NFC]	Kito Cheng	3	-73/+73
2024-12-04	sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729]	Vineet Gupta	1	-0/+4
2024-12-04	RISC-V: Add assert for insn operand out of range access [PR117878][NFC]	Pan Li	1	-0/+6
2024-12-02	RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.	yulong	15	-39/+214
2024-12-02	riscv: Avoid narrowing warning	Andreas Schwab	1	-25/+39
2024-11-30	Support for 64-bit location_t: Backend parts	Lewis Hyatt	1	-2/+1
2024-11-29	[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.	Mariam Arutunian	5	-0/+233
2024-11-29	RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.	yulong	16	-18/+740
2024-11-29	__builtin_prefetch fixes [PR117608]	Jakub Jelinek	1	-1/+2
2024-11-27	diagnostics: replace %<%s%> with %qs [PR104896]	David Malcolm	1	-1/+1
2024-11-26	RISC-V: avlprop: Do not propagate VL from slidedown.	Robin Dapp	1	-1/+2
2024-11-25	Regeernate .opt.urls after nios2 removal	Andrew Pinski	1	-1/+1
2024-11-25	RISC-V: Ensure vtype for full-register moves [PR117544].	Robin Dapp	1	-7/+84
2024-11-25	RISC-V: Use dynamic shadow offset	Kito Cheng	1	-4/+14
2024-11-25	RISC-V: Minimal support for svvptc extension.	Dongyan Chen	1	-0/+2
2024-11-24	opt.url: Regenerate the .opt.urls files	Andrew Pinski	1	-1/+1
2024-11-22	build: Remove INCLUDE_MEMORY [PR117737]	Andrew Pinski	6	-6/+0
2024-11-22	[RISC-V][PR target/109279] Improve RISC-V constant synthesis	Jeff Law	1	-0/+28
2024-11-21	[RISC-V][PR target/117690] Add missing shift in constant synthesis	Jeff Law	1	-4/+8
2024-11-21	[RISC-V][PR target/116590] Avoid emitting multiple instructions from fmacc pa...	Jeff Law	1	-130/+110
2024-11-20	PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition...	Feng Wang	1	-1/+1
2024-11-20	RISC-V: Add the mini support for SiFive extensions.	yulong	1	-0/+6
2024-11-19	[RISC-V][PR target/117649] Fix branch on masked values splitter	Jeff Law	1	-1/+1
2024-11-19	RISC-V: Tie MUL and DIV masks to the M extension	Dimitar Dimitrov	1	-1/+5
2024-11-19	RISC-V: Load VLS perm indices directly from memory.	Robin Dapp	1	-2/+20
2024-11-18	[committed][RISC-V][PR target/117595] Fix bogus use of simplify_gen_subreg	Jeff Law	2	-2/+2
2024-11-18	RISC-V: Add VLS modes to strided loads.	Robin Dapp	3	-13/+256