riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
40 hours	RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688]	Pan Li	1	-1/+1
40 hours	RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688]	Pan Li	1	-2/+2
40 hours	RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688]	Pan Li	1	-2/+2
40 hours	RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC]	Pan Li	1	-29/+49
3 days	RISC-V: Disable two-source permutes for now [PR117173].	Robin Dapp	2	-1/+16
5 days	RISC-V: Make FRM as global register [PR118103]	Pan Li	1	-1/+3
5 days	[RISC-V][PR target/116256] Improve handling of single bit constants	Jeff Law	2	-4/+11
9 days	Revert "[PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions"	Jeff Law	1	-84/+0
9 days	RISC-V: Unbreak bootstrap.	Robin Dapp	1	-2/+2
9 days	RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not g...	Jin Ma	3	-247/+253
9 days	[RISC-V][PR target/116256] Fix incorrect return value for predicate	Jeff Law	1	-4/+4
10 days	[PR target/114442] Add reservations for all insn types to xiangshan-nanhu model	Jeff Law	1	-0/+12
10 days	[PR target/116256] Fix latent regression in pattern to associate arithmetic t...	Jeff Law	1	-10/+2
10 days	RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov	Jin Ma	1	-2/+2
11 days	RISC-V: Add sifive_vector.h	Kito Cheng	1	-0/+32
12 days	[RISC-V][PR target/116308] Fix generation of initial RTL for atomics	Jeff Law	1	-3/+1
12 days	[PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE...	Jin Ma	1	-1/+2
13 days	RISC-V: Remove unused variable in riscv_file_end function.	Monk Chiang	1	-1/+0
14 days	RISC-V: Add -fcf-protection=[full\|branch\|return] to enable zicfiss, zicfilp.	Monk Chiang	5	-20/+61
14 days	RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension	Monk Chiang	1	-1/+51
14 days	RISC-V: Add Zicfilp ISA extension.	Monk Chiang	8	-36/+377
14 days	RISC-V: Add Zicfiss ISA extension.	Monk Chiang	5	-9/+183
2025-01-16	RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases	Liao Shihua	1	-3/+4
2025-01-16	RISC-V: Update Xsfvfnrclip implementation.	Jiawei	7	-25/+78
2025-01-15	RISC-V: Fix code gen for reduction with length 0 [PR118182]	Kito Cheng	6	-23/+257
2025-01-14	[RISC-V][PR target/118170] Add HF div/sqrt reservation	Anton Blanchard	1	-0/+6
2025-01-14	RISC-V: Fix vsetvl compatibility predicate [PR118154].	Robin Dapp	2	-5/+13
2025-01-13	RISC-V: Expand shift count in Xmode in interleave pattern.	Robin Dapp	1	-3/+4
2025-01-13	RISC-V: Disallow negative step for interleaving [PR117682]	Robin Dapp	1	-2/+9
2025-01-13	RISC-V: Remove zba check in bitwise and ashift reassociation [PR 115921]	Xi Ruoyao	1	-6/+1
2025-01-13	RISC-V: Improve bitwise and ashift reassociation for single-bit immediate wit...	Xi Ruoyao	1	-4/+4
2025-01-13	RISC-V: Fix the result error caused by not updating ratio when using "use_max...	Jin Ma	1	-0/+1
2025-01-13	RISC-V: fix thinko in riscv_register_move_cost ()	Vineet Gupta	1	-2/+1
2025-01-13	RISC-V: Fix program logic errors caused by data truncation on 32-bit host for...	Jin Ma	1	-2/+2
2025-01-09	RISC-V: Refine registered_functions list for rvv overloaded intrinsics.	xuli	1	-13/+21
2025-01-07	RISC-V: vector absolute difference expander [PR117722]	Vineet Gupta	1	-0/+26
2025-01-07	[PATCH] riscv: add mising masking in lrsc expander (PR118137)	Andreas Schwab	1	-0/+1
2025-01-02	Update copyright years.	Jakub Jelinek	79	-79/+79
2024-12-30	[RISC-V][PR target/106544] Avoid ICEs due to bogus asms	Jeff Law	1	-71/+98
2024-12-30	[RISC-V][PR target/118122] Fix modes in recently added risc-v pattern	Jeff Law	1	-12/+12
2024-12-29	[RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern	Jeff Law	1	-12/+0
2024-12-29	[PR target/116720] Fix test for valid mempair operands	Jeff Law	1	-6/+14
2024-12-22	RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]	Pan Li	1	-2/+2
2024-12-21	[RISC-V][PR middle-end/118084] Fix brev based reflection code	Jeff Law	1	-6/+15
2024-12-19	RISC-V: Make vector strided store alias all other memories	Pan Li	1	-10/+9
2024-12-17	[PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)	Oliver Kozul	1	-0/+28
2024-12-17	[PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture	Anton Blanchard	2	-0/+30
2024-12-17	RISC-V: Add new constraint R for register even-odd pairs	Kito Cheng	1	-0/+4
2024-12-17	RISC-V: Implment N modifier for printing the register number rather than the ...	Kito Cheng	1	-0/+23
2024-12-17	RISC-V: Rename internal operand modifier N to n	Kito Cheng	3	-5/+5