riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
25 hours	RISC-V: Fix scalar code-gen of unsigned SAT_MUL	Pan Li	1	-2/+2
6 days	Remove STMT_VINFO_MEMORY_ACCESS_TYPE	Richard Biener	1	-8/+8
6 days	RISC-V: Adding H to the canonical order [PR121312]	Kito Cheng	1	-1/+1
7 days	RISC-V: Generate -mcpu and -mtune options from riscv-cores.def.	Dongyan Chen	3	-2/+119
9 days	Move STMT_VINFO_TYPE to SLP_TREE_TYPE	Richard Biener	1	-6/+6
10 days	RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost	Pan Li	3	-4/+7
11 days	RISC-V: riscv-ext.def: Add allocated group IDs and group bit positions	Christoph Müllner	1	-15/+15
12 days	RISC-V: Prepare dynamic LMUL heuristic for SLP.	Robin Dapp	2	-25/+62
12 days	RISC-V: Remove user-level interrupts	Christoph Müllner	2	-19/+8
12 days	RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers	Christoph Müllner	2	-4/+21
13 days	vect: Add is_gather_scatter argument to misalignment hook.	Robin Dapp	1	-6/+23
13 days	RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr	Pan Li	4	-13/+122
13 days	RISC-V: Rework broadcast handling [PR121073].	Robin Dapp	10	-237/+442
2025-07-22	[RISC-V] Restrict generic-vector-ooo DFA	Jeff Law	1	-30/+55
2025-07-21	[RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md	Jeff Law	2	-2/+3
2025-07-21	[RISC-V] Fix wrong CFA during stack probe	Andreas Schwab	1	-1/+1
2025-07-21	RISC-V: Allow VLS DImode for sat_op vx DImode pattern	Pan Li	1	-15/+15
2025-07-21	RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, ...	Pan Li	2	-2/+89
2025-07-20	RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil	Pan Li	1	-2/+4
2025-07-19	[PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate ...	Paul-Antoine Arras	2	-1/+55
2025-07-19	[PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p ()	Artemiy Volkov	1	-2/+2
2025-07-18	RISC-V: Support RVVDImode for avg3_ceil auto vect	Pan Li	1	-0/+13
2025-07-16	RISC-V: Fix vsetvl merge rule.	Robin Dapp	1	-3/+3
2025-07-16	RISC-V: Support RVVDImode for avg3_floor auto vect	Pan Li	1	-0/+13
2025-07-15	[PATCH v5] RISC-V: Mips P8700 Conditional Move Support.	Umesh Kalappa	8	-37/+154
2025-07-14	[PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR1...	Paul-Antoine Arras	3	-4/+93
2025-07-10	RISC-V: Make zero-stride load broadcast a tunable.	Robin Dapp	7	-34/+133
2025-07-10	[RISC-V] Detect new fusions for RISC-V	Daniel Barboza	1	-1/+382
2025-07-10	Change bellow in comments to below	Jakub Jelinek	1	-1/+1
2025-07-09	RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost	Pan Li	3	-1/+4
2025-07-09	[RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector	Jeff Law	1	-1/+1
2025-07-08	RISC-V: Do not use vsetivli for THeadVector.	Robin Dapp	1	-1/+1
2025-07-08	RISC-V: Ignore non-types in builtin function hash.	Robin Dapp	1	-0/+6
2025-07-08	[PATCH] riscv: allow zero in zacas subword atomic cas	Andreas Schwab	1	-1/+1
2025-07-07	RISC-V: Implement unsigned scalar SAT_MUL from uint128_t	Pan Li	3	-0/+94
2025-07-04	RISC-V: prefetch: fix LRA failing to allocate reg [PR118241]	Vineet Gupta	1	-1/+1
2025-07-04	RISC-V: prefetch: const offset needs to have 5 bits zero, not 4	Vineet Gupta	1	-2/+2
2025-07-04	RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost	Pan Li	3	-2/+5
2025-07-03	[RISC-V] Add basic instrumentation to fusion detection	Shreya Munnangi	1	-16/+64
2025-07-03	[RISC-V][PR target/118886] Refine when two insns are signaled as fusion candi...	Jeff Law	1	-57/+80
2025-07-02	[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]	Alexey Merzlyakov	1	-1/+1
2025-06-30	[RISC-V] Correct CFA notes for stack-clash protection [PR120714]	Alexey Merzlyakov	1	-2/+11
2025-06-30	RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost	Pan Li	3	-1/+3
2025-06-30	RISC-V: Primary vector pipeline model for sifive 7 series	Kito Cheng	1	-1/+136
2025-06-30	RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 p...	Kito Cheng	1	-3/+29
2025-06-30	RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100]	Paul-Antoine Arras	2	-16/+52
2025-06-30	RISC-V: Refactor the function bitmap_union_of_preds_with_entry	Jin Ma	1	-22/+19
2025-06-30	RISC-V: Add pipeline-checker script	Kito Cheng	1	-0/+191
2025-06-26	RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828]	Paul-Antoine Arras	1	-3/+5
2025-06-26	RISC-V: Fix build issue	Kito Cheng	1	-1/+1