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author | Jim Wilson <jimw@sifive.com> | 2018-02-15 01:14:23 +0000 |
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committer | Jim Wilson <wilson@gcc.gnu.org> | 2018-02-14 17:14:23 -0800 |
commit | 10789329789fbb5b87883fca029e745a06ded6a0 (patch) | |
tree | b5e6fe7f7bfd30e38823a79d94d8b8b50f921d6c /gcc/config/riscv | |
parent | 1622ba9cefbc2f3e21e42ed336700dd788f11c5c (diff) | |
download | gcc-10789329789fbb5b87883fca029e745a06ded6a0.zip gcc-10789329789fbb5b87883fca029e745a06ded6a0.tar.gz gcc-10789329789fbb5b87883fca029e745a06ded6a0.tar.bz2 |
RISC-V: Change sp subtracts so prologue stores can compress.
gcc/
* config/riscv/riscv.c (riscv_first_stack_step): Move locals after
first SMALL_OPERAND check. New local min_second_step. Move assert
to where locals are set. Add TARGET_RVC support.
* config/riscv/riscv.h (C_SxSP_BITS, SWSP_REACH, SDSP_REACH): New.
From-SVN: r257681
Diffstat (limited to 'gcc/config/riscv')
-rw-r--r-- | gcc/config/riscv/riscv.c | 30 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.h | 4 |
2 files changed, 28 insertions, 6 deletions
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 4ef7a17..c38f6c3 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3495,25 +3495,43 @@ riscv_output_gpr_save (unsigned mask) /* For stack frames that can't be allocated with a single ADDI instruction, compute the best value to initially allocate. It must at a minimum - allocate enough space to spill the callee-saved registers. */ + allocate enough space to spill the callee-saved registers. If TARGET_RVC, + try to pick a value that will allow compression of the register saves + without adding extra instructions. */ static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame) { - HOST_WIDE_INT min_first_step = frame->total_size - frame->fp_sp_offset; - HOST_WIDE_INT max_first_step = IMM_REACH / 2 - STACK_BOUNDARY / 8; - if (SMALL_OPERAND (frame->total_size)) return frame->total_size; + HOST_WIDE_INT min_first_step = frame->total_size - frame->fp_sp_offset; + HOST_WIDE_INT max_first_step = IMM_REACH / 2 - STACK_BOUNDARY / 8; + HOST_WIDE_INT min_second_step = frame->total_size - max_first_step; + gcc_assert (min_first_step <= max_first_step); + /* As an optimization, use the least-significant bits of the total frame size, so that the second adjustment step is just LUI + ADD. */ - if (!SMALL_OPERAND (frame->total_size - max_first_step) + if (!SMALL_OPERAND (min_second_step) && frame->total_size % IMM_REACH < IMM_REACH / 2 && frame->total_size % IMM_REACH >= min_first_step) return frame->total_size % IMM_REACH; - gcc_assert (min_first_step <= max_first_step); + if (TARGET_RVC) + { + /* If we need two subtracts, and one is small enough to allow compressed + loads and stores, then put that one first. */ + if (IN_RANGE (min_second_step, 0, + (TARGET_64BIT ? SDSP_REACH : SWSP_REACH))) + return MAX (min_second_step, min_first_step); + + /* If we need LUI + ADDI + ADD for the second adjustment step, then start + with the minimum first step, so that we can get compressed loads and + stores. */ + else if (!SMALL_OPERAND (min_second_step)) + return min_first_step; + } + return max_first_step; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 1c1c343..6144e26 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -891,9 +891,13 @@ extern unsigned riscv_stack_boundary; #define SHIFT_RS1 15 #define SHIFT_IMM 20 #define IMM_BITS 12 +#define C_SxSP_BITS 6 #define IMM_REACH (1LL << IMM_BITS) #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1)) #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) +#define SWSP_REACH (4LL << C_SxSP_BITS) +#define SDSP_REACH (8LL << C_SxSP_BITS) + #endif /* ! GCC_RISCV_H */ |