RISC-V: Add and document the "-mno-relax" option

RISC-V relies on aggressive linker relaxation to get good code size.  As
a result no text symbol addresses can be known until link time, which
means that alignment must be handled during the link.  This alignment
pass is essentially just another linker relaxation, so this has the
unfortunate side effect that linker relaxation is required for
correctness on many RISC-V targets.

The RISC-V assembler has supported an ".option norelax" for a long time
because there are situations in which linker relaxation is a bad idea --
the canonical example is when trying to materialize the initial value of
the global pointer into a register, which would otherwise be relaxed to
a NOP.  We've been relying on users who want to disable relaxation for
an entire link to pass "-Wl,--no-relax", but that still relies on the
linker relaxing R_RISCV_ALIGN to handle alignment despite it not being
strictly necessary.

This patch adds a GCC option, "-mno-relax", that disable linker
relaxation by adding ".option norelax" to the top of every generated
assembly file.  The assembler is smart enough to handle alignment at
assemble time for files that have never emitted a relaxable relocation,
so this is sufficient to really disable all relaxations in the linker,
which results in significantly faster link times for large objects.

This also has the side effect of allowing toolchains that don't support
linker relaxation (LLVM and the Linux module loader) to function
correctly.  Toolchains that don't support linker relaxation should
default to "-mno-relax" and error when presented with any R_RISCV_ALIGN
relocation as those need to be handled for correctness.

gcc/ChangeLog

2018-03-13  Palmer Dabbelt  <palmer@sifive.com>

        * config/riscv/riscv.opt (mrelax): New option.
        * config/riscv/riscv.c (riscv_file_start): Emit ".option
        "norelax" when riscv_mrelax is disabled.
        * doc/invoke.texi (RISC-V): Document "-mrelax" and "-mno-relax".

From-SVN: r258499

2 files changed, 10 insertions, 0 deletions

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index c38f6c3..3e81874 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3979,6 +3979,11 @@ riscv_file_start (void)
 
   /* Instruct GAS to generate position-[in]dependent code.  */
   fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no"));
+
+  /* If the user specifies "-mno-relax" on the command line then disable linker
+     relaxation in the assembler.  */
+  if (! riscv_mrelax)
+    fprintf (asm_out_file, "\t.option norelax\n");
 }
 
 /* Implement TARGET_ASM_OUTPUT_MI_THUNK.  Generate rtl rather than asm text
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 581a26b..b37ac75 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -106,6 +106,11 @@ mexplicit-relocs
 Target Report Mask(EXPLICIT_RELOCS)
 Use %reloc() operators, rather than assembly macros, to load addresses.
 
+mrelax
+Target Bool Var(riscv_mrelax) Init(1)
+Take advantage of linker relaxations to reduce the number of instructions
+required to materialize symbol addresses.
+
 Mask(64BIT)
 
 Mask(MUL)