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6 daysLoongArch: Implement scalar isinf, isnormal, and isfinite via fclassXi Ruoyao1-7/+46
Doing so can avoid loading FP constants from the memory. It also partially fixes PR 66262 as fclass does not signal on sNaN. gcc/ChangeLog: * config/loongarch/loongarch.md (extendsidi2): Add ("=r", "f") alternative and use movfr2gr.s for it. The spec clearly states movfr2gr.s sign extends the value to GRLEN. (fclass_<fmt>): Make the result SImode instead of a floating mode. The fclass results are really not FP values. (FCLASS_MASK): New define_int_iterator. (fclass_optab): New define_int_attr. (<FCLASS_MASK:fclass_optab><ANYF:mode>): New define_expand template. gcc/testsuite/ChangeLog: * gcc.target/loongarch/fclass-compile.c: New test. * gcc.target/loongarch/fclass-run.c: New test.
10 daysLoongArch: Provide ashr lshr and ashl RTL pattern for vectors.Lulu Cheng2-6/+8
We support vashr vlshr and vashl. However, in r15-1638 support optimize x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31. To support this optimization, vector ashr lshr and ashl need to be implemented. gcc/ChangeLog: * config/loongarch/loongarch.md (insn): Added rotatert rotr pairs. * config/loongarch/simd.md (rotr<mode>3): Remove to ... (<optab><mode>3): This. gcc/testsuite/ChangeLog: * g++.target/loongarch/vect-ashr-lshr.C: New test.
10 daysLoongArch: Drop vcond{,u} expanders.Lulu Cheng2-68/+0
Optabs vcond{,u} will be removed for GCC 15. Since regtest shows no fallout, dropping the expanders, now. gcc/ChangeLog: PR target/114189 * config/loongarch/lasx.md (vcondu<LASX:mode><ILASX:mode>): Delete. (vcond<LASX:mode><LASX_2:mode>): Likewise. * config/loongarch/lsx.md (vcondu<LSX:mode><ILSX:mode>): Likewise. (vcond<LSX:mode><LSX_2:mode>): Likewise.
10 daysLoongArch: Use iorn and andn standard pattern names.Lulu Cheng4-18/+20
R15-1890 introduced new optabs iorc and andc, and its corresponding internal functions BIT_{ANDC,IORC}, and if targets defines such optabs for vector modes. And in r15-2258 the iorc and andc were renamed to iorn and andn. So we changed the andn and iorn implementation templates to the standard template names. gcc/ChangeLog: * config/loongarch/lasx.md (xvandn<mode>3): Rename to ... (andn<mode>3): This. (xvorn<mode>3): Rename to ... (iorn<mode>3): This. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v): Defined as the modified name. (CODE_FOR_lsx_vorn_v): Likewise. (CODE_FOR_lasx_xvandn_v): Likewise. (CODE_FOR_lasx_xvorn_v): Likewise. (loongarch_expand_builtin_insn): When the builtin function to be called is __builtin_lasx_xvandn or __builtin_lsx_vandn, swap the two operands. * config/loongarch/loongarch.md (<optab>n<mode>): Rename to ... (<optab>n<mode>3): This. * config/loongarch/lsx.md (vandn<mode>3): Rename to ... (andn<mode>3): This. (vorn<mode>3): Rename to ... (iorn<mode>3): This. gcc/testsuite/ChangeLog: * gcc.target/loongarch/lasx-andn-iorn.c: New test. * gcc.target/loongarch/lsx-andn-iorn.c: New test.
2024-08-02LoongArch: Remove gawk extension from a generator script.Yang Yujie1-3/+4
gcc/ChangeLog: * config/loongarch/genopts/gen-evolution.awk: Do not use "length()" to compute the size of an array.
2024-07-31LoongArch: Rework bswap{hi,si,di}2 definitionXi Ruoyao1-36/+43
Per a gcc-help thread we are generating sub-optimal code for __builtin_bswap{32,64}. To fix it: - Use a single revb.d instruction for bswapdi2. - Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT, revb.2h + rotri.w for !TARGET_64BIT. - Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single revb.2w instruction for bswapdi2 (x) r>> 32. Unfortunately I cannot figure out a way to make the compiler generate revb.4h or revh.{2w,d} instructions. gcc/ChangeLog: * config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H, UNSPEC_REVH_D): Remove UNSPECs. (revb_4h, revh_d): Remove define_insn. (revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of an UNSPEC. (revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn. (bswapsi2): Change to define_expand. Only expand to revb.2h + rotri.w if !TARGET_64BIT. (bswapdi2): Change to define_insn of which the output is just a revb.d instruction. gcc/testsuite/ChangeLog: * gcc.target/loongarch/revb.c: New test.
2024-07-31LoongArch: Relax ins_zero_bitmask_operand and remove and<mode>3_alignXi Ruoyao3-28/+2
In r15-1207 I was too stupid to realize we just need to relax ins_zero_bitmask_operand to allow using bstrins for aligning, instead of adding a new split. And, "> 12" in ins_zero_bitmask_operand also makes no sense: it rejects bstrins for things like "x & ~4l" with no good reason. So fix my errors now. gcc/ChangeLog: * config/loongarch/predicates.md (ins_zero_bitmask_operand): Cover more cases that bstrins can benefit. (high_bitmask_operand): Remove. * config/loongarch/constraints.md (Yy): Remove. * config/loongarch/loongarch.md (and<mode>3_align): Remove. gcc/testsuite/ChangeLog: * gcc.target/loongarch/bstrins-4.c: New test.
2024-07-31LoongArch: Expand some SImode operations through "si3_extend" instructions ↵Xi Ruoyao1-22/+109
if TARGET_64BIT We already had "si3_extend" insns and we hoped the fwprop or combine passes can use them to remove unnecessary sign extensions. But this does not always work: for cases like x << 1 | y, the compiler tends to do (sign_extend:DI (ior:SI (ashift:SI (reg:SI $r4) (const_int 1)) (reg:SI $r5))) instead of (ior:DI (sign_extend:DI (ashift:SI (reg:SI $r4) (const_int 1))) (sign_extend:DI (reg:SI $r5))) So we cannot match the ashlsi3_extend instruction here and we get: slli.w $r4,$r4,1 or $r4,$r5,$r4 slli.w $r4,$r4,0 # <= redundant jr $r1 To eliminate this redundant extension we need to turn SImode shift etc. to DImode "si3_extend" operations earlier, when we expand the SImode operation. We are already doing this for addition, now do it for shifts, rotates, substract, multiplication, division, and modulo as well. The bytepick.w definition for TARGET_64BIT needs to be adjusted so it won't be undone by the shift expanding. gcc/ChangeLog: * config/loongarch/loongarch.md (optab): Add (rotatert "rotr"). (<optab:any_shift><mode>3, <optab:any_div><mode>3, sub<mode>3, rotr<mode>3, mul<mode>3): Add a "*" to the insn name so we can redefine the names with define_expand. (*<optab:any_shift>si3_extend): Remove "*" so we can use them in expanders. (*subsi3_extended, *mulsi3_extended): Likewise, also remove the trailing "ed" for consistency. (*<optab:any_div>si3_extended): Add mode for sign_extend to prevent an ICE using it in expanders. (shift_w, arith_w): New define_code_iterator. (<optab:any_w><mode>3): New define_expand. Expand with <optab:any_w>si3_extend for SImode if TARGET_64BIT. (<optab:arith_w><mode>3): Likewise. (mul<mode>3): Expand to mulsi3_extended for SImode if TARGET_64BIT and ISA_HAS_DIV32. (<optab:any_div><mode>3): Expand to <optab:any_div>si3_extended for SImode if TARGET_64BIT. (rotl<mode>3): Expand to rotrsi3_extend for SImode if TARGET_64BIT. (bytepick_w_<bytepick_imm>): Add mode for lshiftrt and ashift. (bitsize, bytepick_imm, bytepick_w_ashift_amount): New define_mode_attr. (bytepick_w_<bytepick_imm>_extend): Adjust for the RTL change caused by 32-bit shift expanding. Now bytepick_imm only covers 2 and 3, separate one remaining case to ... (bytepick_w_1_extend): ... here, new define_insn. gcc/testsuite/ChangeLog: * gcc.target/loongarch/bitwise_extend.c: New test.
2024-07-20LoongArch: Organize the code related to split move and merge the same functions.Lulu Cheng3-169/+58
gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_split_128bit_move): Delete. (loongarch_split_128bit_move_p): Delete. (loongarch_split_256bit_move): Delete. (loongarch_split_256bit_move_p): Delete. (loongarch_split_vector_move): Add a function declaration. * config/loongarch/loongarch.cc (loongarch_vector_costs::finish_cost): Adjust the code formatting. (loongarch_split_vector_move_p): Merge loongarch_split_128bit_move_p and loongarch_split_256bit_move_p. (loongarch_split_move_p): Merge code. (loongarch_split_move): Likewise. (loongarch_split_128bit_move_p): Delete. (loongarch_split_256bit_move_p): Delete. (loongarch_split_128bit_move): Delete. (loongarch_split_vector_move): Merge loongarch_split_128bit_move and loongarch_split_256bit_move. (loongarch_split_256bit_move): Delete. (loongarch_global_init): Remove the extra semicolon at the end of the function. * config/loongarch/loongarch.md (*movdf_softfloat): Added a new condition TARGET_64BIT.
2024-07-12LoongArch: Remove unreachable codes.Lulu Cheng2-148/+8
gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_split_move): Delete. (loongarch_hard_regno_mode_ok_uncached): Likewise. * config/loongarch/loongarch.md (move_doubleword_fpr<mode>): Likewise. (load_low<mode>): Likewise. (load_high<mode>): Likewise. (store_word<mode>): Likewise. (movgr2frh<mode>): Likewise. (movfrh2gr<mode>): Likewise.
2024-07-12LoongArch: TFmode is not allowed to be stored in the float register.Lulu Cheng2-8/+1
PR target/115752 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_hard_regno_mode_ok_uncached): Replace UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE. * config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr115752.c: New test.
2024-07-02LoongArch: Define loongarch_insn_cost and set the cost of movcf2gr and movgr2cf.Lulu Cheng1-0/+29
The following two FAIL items have been fixed: FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movcf2fr\\t\\\\\$f[0-9]+,\\\\\$fcc FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movfr2gr\\\\.s\\t\\\\\$r4 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_insn_cost): New function. (TARGET_INSN_COST): New macro.
2024-06-27LoongArch: NFC: Dedup and sort the comment in loongarch_print_operand_relocXi Ruoyao1-9/+1
gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_print_operand_reloc): Dedup and sort the comment describing modifiers.
2024-06-27LoongArch: Tweak IOR rtx_cost for bstrinsXi Ruoyao1-17/+56
Consider c &= 0xfff; a &= ~0xfff; b &= ~0xfff; a |= c; b |= c; This can be done with 2 bstrins instructions. But we need to recognize it in loongarch_rtx_costs or the compiler will not propagate "c & 0xfff" forward. gcc/ChangeLog: * config/loongarch/loongarch.cc: (loongarch_use_bstrins_for_ior_with_mask): Split the main logic into ... (loongarch_use_bstrins_for_ior_with_mask_1): ... here. (loongarch_rtx_costs): Special case for IOR those can be implemented with bstrins. gcc/testsuite/ChangeLog; * gcc.target/loongarch/bstrins-3.c: New test.
2024-06-25Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_typeKewen Lin2-7/+21
Currently how we determine which mode will be used for a floating point type is that for a given type precision (size) call mode_for_size to get the first mode which has this size in the specified class. On Powerpc, we have three modes (TF/KF/IF) having the same mode precision 128 (see[1]), so the processing forces us to have to place TF at the first place, it would require us to make more adjustment in some generic code to avoid some unexpected mode conversions and it would be even worse if we get rid of TF eventually one day. And as Joseph pointed out in [2], "floating types should have their mode, not a poorly defined precision value", as Joseph and Richi suggested, this patch is to introduce one hook mode_for_floating_type which returns the corresponding mode for type float, double or long double. The default implementation returns SFmode for float and DFmode for double or long double. For ports which need special treatment, there are some other patches for their own port specific implementation (referring to how {,LONG_}DOUBLE_TYPE_SIZE get used there). For all generic uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE, depending on the context, some of them are replaced with TYPE_PRECISION of the according type node, some other are replaced with GET_MODE_PRECISION on the mode from mode_for_floating_type. This patch also poisons {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE, so most defines of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE in port specific are removed, but there are still some which are good to be kept for readability then they get renamed with port specific prefix. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651017.html [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651209.html gcc/jit/ChangeLog: * jit-recording.cc (recording::memento_of_get_type::get_size): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE. gcc/ChangeLog: * coretypes.h (enum tree_index): Forward declaration. * defaults.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * doc/rtl.texi: Update document by replacing {FLOAT,DOUBLE}_TYPE_SIZE with C type {float,double}. * doc/tm.texi.in: Document new hook mode_for_floating_type, remove document entries for {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE and update document for WIDEST_HARDWARE_FP_SIZE. * doc/tm.texi: Regenerate. * emit-rtl.cc (init_emit_once): Replace DOUBLE_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_DOUBLE_TYPE. * real.h (REAL_VALUE_TO_TARGET_LONG_DOUBLE): Use TYPE_PRECISION of long_double_type_node to replace LONG_DOUBLE_TYPE_SIZE. * system.h (FLOAT_TYPE_SIZE): Poison. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * target.def (mode_for_floating_type): New hook. * targhooks.cc (default_mode_for_floating_type): New function. (default_scalar_mode_supported_p): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE. * targhooks.h (default_mode_for_floating_type): New declaration. * tree-core.h (enum tree_index): Specify underlying type unsigned to sync with forward declaration in coretypes.h. (NUM_FLOATN_TYPES): Explicitly convert to int. (NUM_FLOATNX_TYPES): Likewise. (NUM_FLOATN_NX_TYPES): Likewise. * tree.cc (build_common_tree_nodes): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE and set type mode accordingly. * config/arc/arc.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/bpf/bpf.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/epiphany/epiphany.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/fr30/fr30.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/frv/frv.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/ft32/ft32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/gcn/gcn.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/iq2000/iq2000.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/lm32/lm32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/m32c/m32c.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/m32r/m32r.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/microblaze/microblaze.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/mmix/mmix.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/moxie/moxie.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/msp430/msp430.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nds32/nds32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nios2/nios2.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nvptx/nvptx.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/or1k/or1k.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pdp11/pdp11.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pru/pru.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/stormy16/stormy16.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/visium/visium.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/xtensa/xtensa.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rs6000/rs6000.cc (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (rs6000_c_mode_for_floating_type): New function. * config/rs6000/rs6000.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/aarch64/aarch64.cc (aarch64_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/aarch64/aarch64.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/alpha/alpha.cc (alpha_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/alpha/alpha.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/avr/avr.cc (avr_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/avr/avr.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/i386/i386.cc (ix86_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/i386/i386.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/ia64/ia64.cc (ia64_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/ia64/ia64.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/riscv/riscv.cc (riscv_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/riscv/riscv.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rl78/rl78.cc (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (rl78_c_mode_for_floating_type): New function. * config/rl78/rl78.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rx/rx.cc (rx_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/rx/rx.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/s390/s390.cc (s390_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/s390/s390.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/sh/sh.cc (sh_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/sh/sh.h (LONG_DOUBLE_TYPE_SIZE): Remove. * config/h8300/h8300.cc (h8300_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/h8300/h8300.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Remove. (DOUBLE_TYPE_MODE): New macro. * config/h8300/linux.h (DOUBLE_TYPE_SIZE): Remove. (DOUBLE_TYPE_MODE): New macro. * config/loongarch/loongarch.cc (loongarch_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/loongarch/loongarch.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (LA_LONG_DOUBLE_TYPE_SIZE): ... this. (UNITS_PER_FPVALUE): Replace LONG_DOUBLE_TYPE_SIZE with LA_LONG_DOUBLE_TYPE_SIZE. (MAX_FIXED_MODE_SIZE): Likewise. (STRUCTURE_SIZE_BOUNDARY): Likewise. (BIGGEST_ALIGNMENT): Likewise. * config/m68k/m68k.cc (m68k_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/m68k/m68k.h (LONG_DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_MODE): New macro. * config/m68k/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_MODE): New macro. * config/mips/mips.cc (mips_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/mips/mips.h (UNITS_PER_FPVALUE): Replace LONG_DOUBLE_TYPE_SIZE with MIPS_LONG_DOUBLE_TYPE_SIZE. (MAX_FIXED_MODE_SIZE): Likewise. (STRUCTURE_SIZE_BOUNDARY): Likewise. (BIGGEST_ALIGNMENT): Likewise. (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (MIPS_LONG_DOUBLE_TYPE_SIZE): ... this. * config/mips/n32-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (MIPS_LONG_DOUBLE_TYPE_SIZE): ... this. * config/pa/pa.cc (pa_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (pa_scalar_mode_supported_p): Rename FLOAT_TYPE_SIZE to PA_FLOAT_TYPE_SIZE, rename DOUBLE_TYPE_SIZE to PA_DOUBLE_TYPE_SIZE and rename LONG_DOUBLE_TYPE_SIZE to PA_LONG_DOUBLE_TYPE_SIZE. * config/pa/pa.h (PA_FLOAT_TYPE_SIZE): New macro. (PA_DOUBLE_TYPE_SIZE): Likewise. (PA_LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pa/pa-64.h (FLOAT_TYPE_SIZE): Rename to ... (PA_FLOAT_TYPE_SIZE): ... this. (DOUBLE_TYPE_SIZE): Rename to ... (PA_DOUBLE_TYPE_SIZE): ... this. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (PA_LONG_DOUBLE_TYPE_SIZE): ... this. * config/pa/pa-hpux.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (PA_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sparc.cc (sparc_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. (sparc_type_code): Replace FLOAT_TYPE_SIZE with TYPE_PRECISION of float_type_node. * config/sparc/sparc.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. * config/sparc/freebsd.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/linux.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/linux64.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/openbsd64.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sol2.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sp-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sp64-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/bfin/bfin.h (FLOAT_TYPE_SIZE): Rename to ... (BFIN_FLOAT_TYPE_SIZE): ... this. (DOUBLE_TYPE_SIZE): Rename to ... (BFIN_DOUBLE_TYPE_SIZE): ... this. (LONG_DOUBLE_TYPE_SIZE): Remove. (UNITS_PER_FLOAT): Replace FLOAT_TYPE_SIZE with BFIN_FLOAT_TYPE_SIZE. (UNITS_PER_DOUBLE): Replace DOUBLE_TYPE_SIZE with BFIN_DOUBLE_TYPE_SIZE.
2024-06-12LoongArch: Use bstrins for "value & (-1u << const)"Xi Ruoyao3-0/+26
A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and pair, and twice fast as a srli/slli pair. When the src reg and the dst reg happens to be the same, the move instruction can be optimized away. gcc/ChangeLog: * config/loongarch/predicates.md (high_bitmask_operand): New predicate. * config/loongarch/constraints.md (Yy): New constriant. * config/loongarch/loongarch.md (and<mode>3_align): New define_insn_and_split. gcc/testsuite/ChangeLog: * gcc.target/loongarch/bstrins-1.c: New test. * gcc.target/loongarch/bstrins-2.c: New test.
2024-06-12LoongArch: Fix mode size comparision in loongarch_expand_conditional_moveXi Ruoyao1-1/+1
We were comparing a mode size with word_mode, but word_mode is an enum value thus this does not really make any sense. (Un)luckily E_DImode happens to be 8 so this seemed to work, but let's make it correct so it won't blow up when we add LA32 support or add another machine mode... gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Compare mode size with UNITS_PER_WORD instead of word_mode.
2024-05-31Fix some opindex for some options [PR115022]Andrew Pinski1-1/+1
While looking at the index I noticed that some options had `-` in the front for the index which is wrong. And then I noticed there was no index for `mcmodel=` for targets or had used `-mcmodel` incorrectly. This fixes both of those and regnerates the urls files see that `-mcmodel=` option now has an url associated with it. gcc/ChangeLog: PR target/115022 * doc/invoke.texi (fstrub=disable): Fix opindex. (minline-memops-threshold): Fix opindex. (mcmodel=): Add opindex and fix them. * common.opt.urls: Regenerate. * config/aarch64/aarch64.opt.urls: Regenerate. * config/bpf/bpf.opt.urls: Regenerate. * config/i386/i386.opt.urls: Regenerate. * config/loongarch/loongarch.opt.urls: Regenerate. * config/nds32/nds32-elf.opt.urls: Regenerate. * config/nds32/nds32-linux.opt.urls: Regenerate. * config/or1k/or1k.opt.urls: Regenerate. * config/riscv/riscv.opt.urls: Regenerate. * config/rs6000/aix64.opt.urls: Regenerate. * config/rs6000/linux64.opt.urls: Regenerate. * config/sparc/sparc.opt.urls: Regenerate. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-05-28LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move ↵Xi Ruoyao1-5/+12
[PR115169] gcc/ChangeLog: PR target/115169 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Guard REGNO with REG_P.
2024-04-27LoongArch: Add constraints for bit string operation define_insn_and_split's ↵Xi Ruoyao1-8/+8
[PR114861] Without the constrants, the compiler attempts to use a stack slot as the target, causing an ICE building the kernel with -Os: drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:3144:1: error: could not split insn (insn:TI 1764 67 1745 (set (mem/c:DI (reg/f:DI 3 $r3) [707 %sfp+-80 S8 A64]) (and:DI (reg/v:DI 28 $r28 [orig:422 raster_config ] [422]) (const_int -50331649 [0xfffffffffcffffff]))) "drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c":1386:21 111 {*bstrins_di_for_mask} (nil)) Add these constrants to fix the issue. gcc/ChangeLog: PR target/114861 * config/loongarch/loongarch.md (bstrins_<mode>_for_mask): Add constraints for operands. (bstrins_<mode>_for_ior_mask): Likewise. gcc/testsuite/ChangeLog: PR target/114861 * gcc.target/loongarch/pr114861.c: New test.
2024-04-23LoongArch: Define builtin macros for ISA evolutionsYang Yujie10-94/+397
Detailed description of these definitions can be found at https://github.com/loongson/la-toolchain-conventions, which the LoongArch GCC port aims to conform to. gcc/ChangeLog: * config.gcc: Add loongarch-evolution.o. * config/loongarch/genopts/genstr.sh: Enable generation of loongarch-evolution.[cc,h]. * config/loongarch/t-loongarch: Likewise. * config/loongarch/genopts/gen-evolution.awk: New file. * config/loongarch/genopts/isa-evolution.in: Mark ISA version of introduction for each ISA evolution feature. * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins): Define builtin macros for enabled ISA evolutions and the ISA version. * config/loongarch/loongarch-cpu.cc: Use loongarch-evolution.h. * config/loongarch/loongarch.h: Likewise. * config/loongarch/loongarch-cpucfg-map.h: Delete. * config/loongarch/loongarch-evolution.cc: New file. * config/loongarch/loongarch-evolution.h: New file. * config/loongarch/loongarch-opts.h (ISA_HAS_FRECIPE): Define. (ISA_HAS_DIV32): Likewise. (ISA_HAS_LAM_BH): Likewise. (ISA_HAS_LAMCAS): Likewise. (ISA_HAS_LD_SEQ_SA): Likewise.
2024-04-23LoongArch: Define ISA versionsYang Yujie12-131/+246
These ISA versions are defined as -march= parameters and are recommended for building binaries for distribution. Detailed description of these definitions can be found at https://github.com/loongson/la-toolchain-conventions, which the LoongArch GCC port aims to conform to. gcc/ChangeLog: * config.gcc: Make la64v1.0 the default ISA preset of the lp64d ABI. * config/loongarch/genopts/loongarch-strings: Define la64v1.0, la64v1.1. * config/loongarch/genopts/loongarch.opt.in: Likewise. * config/loongarch/loongarch-c.cc (LARCH_CPP_SET_PROCESSOR): Likewise. (loongarch_cpu_cpp_builtins): Likewise. * config/loongarch/loongarch-cpu.cc (get_native_prid): Likewise. (fill_native_cpu_config): Likewise. * config/loongarch/loongarch-def.cc (array_tune): Likewise. * config/loongarch/loongarch-def.h: Likewise. * config/loongarch/loongarch-driver.cc (driver_set_m_parm): Likewise. (driver_get_normalized_m_opts): Likewise. * config/loongarch/loongarch-opts.cc (default_tune_for_arch): Likewise. (TUNE_FOR_ARCH): Likewise. (arch_str): Likewise. (loongarch_target_option_override): Likewise. * config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Likewise. (TARGET_uARCH_LA664): Likewise. * config/loongarch/loongarch-str.h (STR_CPU_ABI_DEFAULT): Likewise. (STR_ARCH_ABI_DEFAULT): Likewise. (STR_TUNE_GENERIC): Likewise. (STR_ARCH_LA64V1_0): Likewise. (STR_ARCH_LA64V1_1): Likewise. * config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width): Likewise. (loongarch_asm_code_end): Likewise. * config/loongarch/loongarch.opt: Likewise. * doc/invoke.texi: Likewise.
2024-04-16LoongArch: Add indexes for some compilation options.Lulu Cheng1-2/+7
gcc/ChangeLog: * config/loongarch/loongarch.opt.urls: Regenerate. * config/mn10300/mn10300.opt.urls: Likewise. * config/msp430/msp430.opt.urls: Likewise. * config/nds32/nds32-elf.opt.urls: Likewise. * config/nds32/nds32-linux.opt.urls: Likewise. * config/nds32/nds32.opt.urls: Likewise. * config/pru/pru.opt.urls: Likewise. * config/riscv/riscv.opt.urls: Likewise. * config/rx/rx.opt.urls: Likewise. * config/sh/sh.opt.urls: Likewise. * config/sparc/sparc.opt.urls: Likewise. * doc/invoke.texi: Add indexes for some compilation options.
2024-04-09LoongArch: Enable switchable targetYang Yujie3-17/+101
This patch fixes the back-end context switching in cases where functions should be built with their own target contexts instead of the global one, such as LTO linking and functions with target attributes (TBD). PR target/113233 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_reg_init): Reinitialize the loongarch_regno_mode_ok cache. (loongarch_option_override): Same. (loongarch_save_restore_target_globals): Restore target globals. (loongarch_set_current_function): Restore the target contexts for functions. (TARGET_SET_CURRENT_FUNCTION): Define. * config/loongarch/loongarch.h (SWITCHABLE_TARGET): Enable switchable target context. * config/loongarch/loongarch-builtins.cc (loongarch_init_builtins): Initialize all builtin functions at startup. (loongarch_expand_builtin): Turn assertion of builtin availability into a test. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Define condition loongarch_sx_as. * gcc.dg/lto/pr113233_0.c: New test.
2024-04-08LoongArch: Set default alignment for functions jumps and loops [PR112919].Lulu Cheng3-16/+36
Xi Ruoyao set the alignment rules under LA464 in commit r14-1839, but the macro ASM_OUTPUT_ALIGN_WITH_NOP was removed in R14-4674, which affected the alignment rules. So I set different aligns on LA464 and LA664 again to test the performance of spec2006, and modify the alignment based on the test results. gcc/ChangeLog: PR target/112919 * config/loongarch/loongarch-def.cc (la664_align): Newly defined function that sets alignment rules under the LA664 microarchitecture. * config/loongarch/loongarch-opts.cc (loongarch_target_option_override): If not optimizing for size, set the default alignment to what the target wants. * config/loongarch/loongarch-tune.h (struct loongarch_align): Add new member variables jump and loop.
2024-04-03LoongArch: Remove unused code.Jiahao Xu4-171/+9
gcc/ChangeLog: * config/loongarch/lasx.md: Remove unused code. * config/loongarch/loongarch-protos.h (loongarch_split_lsx_copy_d): Remove. (loongarch_split_lsx_insert_d): Ditto. (loongarch_split_lsx_fill_d): Ditto. * config/loongarch/loongarch.cc (loongarch_split_lsx_copy_d): Ditto. (loongarch_split_lsx_insert_d): Ditto. (loongarch_split_lsx_fill_d): Ditto. * config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter. (lsx_vpickve2gr_<lsxfmt_f>): Ditto. (abs<mode>2): Remove expander. (vabs<mode>2): Rename 2 abs<mode>2. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lsx/lsx-abs.c: New test.
2024-04-02LoongArch: Fix missing plugin headerYang Yujie1-2/+3
gcc/ChangeLog: * config/loongarch/t-loongarch: Add loongarch-def-arrays.h to OPTION_H_EXTRA.
2024-04-02LoongArch: Add support for TLS descriptors.mengqinggang9-14/+154
Add support for TLS descriptors on normal code model and extreme code model. Normal code model instruction sequence: -mno-explicit-relocs: la.tls.desc $r4, s add.d $r12, $r4, $r2 -mexplicit-relocs: pcalau12i $r4,%desc_pc_hi20(s) addi.d $r4,$r4,%desc_pc_lo12(s) ld.d $r1,$r4,%desc_ld(s) jirl $r1,$r1,%desc_call(s) add.d $r12, $r4, $r2 Extreme code model instruction sequence: -mno-explicit-relocs: la.tls.desc $r4, $r12, s add.d $r12, $r4, $r2 -mexplicit-relocs: pcalau12i $r4,%desc_pc_hi20(s) addi.d $r12,$r0,%desc_pc_lo12(s) lu32i.d $r12,%desc64_pc_lo20(s) lu52i.d $r12,$r12,%desc64_pc_hi12(s) add.d $r4,$r4,$r12 ld.d $r1,$r4,%desc_ld(s) jirl $r1,$r1,%desc_call(s) add.d $r12, $r4, $r2 The default is still traditional TLS model, but can be configured with --with-tls={trad,desc}. The default can change to TLS descriptors once libc and LLVM support this. gcc/ChangeLog: * config.gcc: Add --with-tls option to change TLS flavor. * config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to configure TLS flavor. * config/loongarch/loongarch-def.h (struct loongarch_target): Add tls_dialect. * config/loongarch/loongarch-driver.cc (la_driver_init): Add tls flavor. * config/loongarch/loongarch-opts.cc (loongarch_init_target): Add tls_dialect. (loongarch_config_target): Ditto. (loongarch_update_gcc_opt_status): Ditto. * config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto. (TARGET_TLS_DESC): New define. * config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS DESC instructions sequence length. (loongarch_legitimize_tls_address): New TLS DESC instruction sequence. (loongarch_option_override_internal): Add la_opt_tls_dialect. (loongarch_option_restore): Add la_target.tls_dialect. * config/loongarch/loongarch.md (@got_load_tls_desc<mode>): Normal code model for TLS DESC. (got_load_tls_desc_off64): Extreme cmode model for TLS DESC. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch.opt.urls: Ditto. * doc/invoke.texi: Add a description of the compilation option '-mtls-dialect={trad,desc}'. gcc/testsuite/ChangeLog: * gcc.target/loongarch/cmodel-extreme-1.c: Add -mtls-dialect=trad. * gcc.target/loongarch/cmodel-extreme-2.c: Ditto. * gcc.target/loongarch/explicit-relocs-auto-tls-ld-gd.c: Ditto. * gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c: Ditto. * gcc.target/loongarch/func-call-medium-1.c: Ditto. * gcc.target/loongarch/func-call-medium-2.c: Ditto. * gcc.target/loongarch/func-call-medium-3.c: Ditto. * gcc.target/loongarch/func-call-medium-4.c: Ditto. * gcc.target/loongarch/tls-extreme-macro.c: Ditto. * gcc.target/loongarch/tls-gd-noplt.c: Ditto. * gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c: New test. * gcc.target/loongarch/explicit-relocs-auto-tls-desc.c: New test. * gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c: New test. * gcc.target/loongarch/explicit-relocs-tls-desc.c: New test. Co-authored-by: Lulu Cheng <chenglulu@loongson.cn> Co-authored-by: Xi Ruoyao <xry111@xry111.site>
2024-04-02LoongArch: Regenerate loongarch.opt.urls.Lulu Cheng1-2/+17
Fixes: d28ea8e5a704 ("LoongArch: Split loongarch_option_override_internal into smaller procedures") gcc/ChangeLog: * config/loongarch/loongarch.opt.urls: Regenerate.
2024-04-01LoongArch: Split loongarch_option_override_internal into smaller proceduresYang Yujie7-236/+342
gcc/ChangeLog: * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as aliases to -mrecip={all,none}, respectively. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to... (ABI_FPU64_P): ...this. (ABI_FPU_32): Rename to... (ABI_FPU32_P): ...this. (ABI_FPU_NONE): Rename to... (ABI_NOFPU_P): ...this. (ABI_LP64_P): Define. * config/loongarch/loongarch.cc (loongarch_init_print_operand_punct): Merged into loongarch_global_init. (loongarch_cpu_option_override): Renamed to loongarch_target_option_override. (loongarch_option_override_internal): Move the work after loongarch_config_target into loongarch_target_option_override. (loongarch_global_init): Define. (INIT_TARGET_FLAG): Move to loongarch-opts.cc. (loongarch_option_override): Call loongarch_global_init separately. * config/loongarch/loongarch-opts.cc (loongarch_parse_mrecip_scheme): Split the parsing of -mrecip=<string> from loongarch_option_override_internal. (loongarch_generate_mrecip_scheme): Define. Split from loongarch_option_override_internal. (loongarch_target_option_override): Define. Renamed from loongarch_cpu_option_override. (loongarch_init_misc_options): Define. Split from loongarch_option_override_internal. (INIT_TARGET_FLAG): Move from loongarch.cc. * config/loongarch/loongarch-opts.h (loongarch_target_option_override): New prototype. (loongarch_parse_mrecip_scheme): New prototype. (loongarch_init_misc_options): New prototype. (TARGET_ABI_LP64): Simplify with ABI_LP64_P. * config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify. Do not reference specific CPU architecture (LA664). (TARGET_RECIP_SQRT): Same. (TARGET_RECIP_RSQRT): Same. (TARGET_RECIP_VEC_DIV): Same. (TARGET_RECIP_VEC_SQRT): Same. (TARGET_RECIP_VEC_RSQRT): Same.
2024-03-21LoongArch: Fix a typo [PR 114407]Xi Ruoyao1-1/+1
gcc/ChangeLog: PR target/114407 * config/loongarch/loongarch-opts.cc (loongarch_config_target): Fix typo in diagnostic message, enabing -> enabling.
2024-03-20LoongArch: Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros.Chenghui Pan2-10/+7
These macros are completely same in definition, so we can keep the previous one and eliminate later one. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros. (loongarch_hard_regno_nregs): Ditto. (loongarch_class_max_nregs): Ditto. (loongarch_get_separate_components): Ditto. (loongarch_process_components): Ditto. * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto. (UNITS_PER_HWFPVALUE): Ditto. (UNITS_PER_FPVALUE): Ditto.
2024-03-20LoongArch: Change loongarch_expand_vec_cmp()'s return type from bool to void.Chenghui Pan4-11/+6
This function is always return true at the end of function implementation, so the return value is useless. gcc/ChangeLog: * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking of loongarch_expand_vec_cmp()'s return value. (vec_cmpu<ILASX:mode><mode256_i>): Ditto. * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto. (vec_cmpu<ILSX:mode><mode_i>): Ditto. * config/loongarch/loongarch-protos.h (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return type from bool to void. * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
2024-03-20LoongArch: Remove unused/useless definitions.Chenghui Pan2-31/+0
This patch removes some unnecessary definitions of target hook functions according to the documentation of GCC. gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_cfun_has_cprestore_slot_p): Delete. (loongarch_adjust_insn_length): Delete. (current_section_name): Delete. (loongarch_split_symbol_type): Delete. * config/loongarch/loongarch.cc (loongarch_case_values_threshold): Delete. (loongarch_spill_class): Delete. (TARGET_OPTAB_SUPPORTED_P): Delete. (TARGET_CASE_VALUES_THRESHOLD): Delete. (TARGET_SPILL_CLASS): Delete.
2024-03-19LoongArch: Fix C23 (...) functions returning large aggregates [PR114175]Xi Ruoyao1-1/+7
We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and there is nothing to advance, but that is not the case for (...) functions returning by hidden reference which have one such artificial argument. This is causing gcc.dg/c23-stdarg-6.c and gcc.dg/c23-stdarg-8.c to fail. Fix the issue by checking if arg.type is NULL, as r14-9503 explains. gcc/ChangeLog: PR target/114175 * config/loongarch/loongarch.cc (loongarch_setup_incoming_varargs): Only skip loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL.
2024-03-15LoongArch: Remove masking process for operand 3 of xvpermi.q.Chenghui Pan1-5/+0
The behavior of non-zero unused bits in xvpermi.q instruction's third operand is undefined on LoongArch, according to our discussion (https://github.com/llvm/llvm-project/pull/83540), we think that keeping original insn operand as unmodified state is better solution. This patch partially reverts 7b158e036a95b1ab40793dd53bed7dbd770ffdaf. gcc/ChangeLog: * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>): Remove masking of operand 3. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-xvpermi_q.c: Reposition operand 3's value into instruction's defined accept range.
2024-03-14LoongArch: Remove unused and incorrect "sge<u>_<X:mode><GPR:mode>" define_insnXi Ruoyao1-10/+0
If this insn is really used, we'll have something like slti $r4,$r0,$r5 in the code. The assembler will reject it because slti wants 2 register operands and 1 immediate operand. But we've not got any bug report for this, indicating this define_insn is unused at all. Note that do_store_flag (in expr.cc) is already converting x >= 1 to x > 0 unconditionally, so this define_insn is indeed unused and we can just remove it. gcc/ChangeLog: * config/loongarch/loongarch.md (any_ge): Remove. (sge<u>_<X:mode><GPR:mode>): Remove.
2024-03-09LoongArch: Emit R_LARCH_RELAX for TLS IE with non-extreme code model to ↵Xi Ruoyao2-2/+15
allow the IE to LE linker relaxation In Binutils we need to make IE to LE relaxation only allowed when there is an R_LARCH_RELAX after R_LARCH_TLE_IE_PC_{HI20,LO12} so an invalid "partial" relaxation won't happen with the extreme code model. So if we are emitting %ie_pc_{hi20,lo12} in a non-extreme code model, emit an R_LARCH_RELAX to allow the relaxation. The IE to LE relaxation does not require the pcalau12i and the ld instruction to be adjacent, so we don't need to limit ourselves to use the macro. For the distro maintainers backporting changes: this change depends on r14-8721, without r14-8721 R_LARCH_RELAX can be emitted mistakenly in the extreme code model. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_print_operand_reloc): Support 'Q' for R_LARCH_RELAX for TLS IE. (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS IE. * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/tls-ie-relax.c: New test. * gcc.target/loongarch/tls-ie-norelax.c: New test. * gcc.target/loongarch/tls-ie-extreme.c: New test.
2024-03-09LoongArch: Fixed an issue with the implementation of the template ↵Lulu Cheng1-11/+35
atomic_compare_and_swapsi. If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to be implemented through "ll.w+sc.w". In the implementation of the instruction sequence, it is necessary to determine whether the two registers are equal. Since LoongArch's comparison instructions do not distinguish between 32-bit and 64-bit, the two operand registers that need to be compared are symbolically extended, and one of the operand registers is obtained from memory through the "ll.w" instruction, which can ensure that the symbolic expansion is carried out. However, the value of the other operand register is not guaranteed to be the value of the sign extension. gcc/ChangeLog: * config/loongarch/sync.md (atomic_cas_value_strong<mode>): In loongarch64, a sign extension operation is added when operands[2] is a register operand and the mode is SImode. gcc/testsuite/ChangeLog: * g++.target/loongarch/atomic-cas-int.C: New test.
2024-03-07LoongArch: Use /lib instead of /lib64 as the library search path for MUSL.Yang Yujie2-1/+26
gcc/ChangeLog: * config.gcc: Add a case for loongarch*-*-linux-musl*. * config/loongarch/linux.h: Disable the multilib-compatible treatment for *musl* targets. * config/loongarch/musl.h: New file.
2024-03-05LoongArch: Allow s9 as a register aliasXi Ruoyao1-0/+1
The psABI allows using s9 as an alias of r22. gcc/ChangeLog: * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add s9 as an alias of r22. gcc/testsuite/ChangeLog: * gcc.target/loongarch/regname-fp-s9.c: New test.
2024-02-29LoongArch: Remove unneeded sign extension after crc/crcc instructionsXi Ruoyao1-0/+11
The specification of crc/crcc instructions is clear that the output is sign-extended to GRLEN. Add a define_insn to tell the compiler this fact and allow it to remove the unneeded sign extension on crc/crcc output. As crc/crcc instructions are usually used in a tight loop, this should produce a significant performance gain. gcc/ChangeLog: * config/loongarch/loongarch.md (loongarch_<crc>_w_<size>_w_extended): New define_insn. gcc/testsuite/ChangeLog: * gcc.target/loongarch/crc-sext.c: New test;
2024-02-29LoongArch: NFC: Deduplicate crc instruction definesXi Ruoyao1-13/+5
Introduce an iterator for UNSPEC_CRC and UNSPEC_CRCC to make the next change easier. gcc/ChangeLog: * config/loongarch/loongarch.md (CRC): New define_int_iterator. (crc): New define_int_attr. (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify into ... (loongarch_<crc>_w_<size>_w): ... here.
2024-02-18LoongArch: Remove redundant symbol type conversions in larchintrin.h.Lulu Cheng1-36/+33
gcc/ChangeLog: * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant symbol type conversions. (__cacop_d): Likewise. (__cpucfg): Likewise. (__asrtle_d): Likewise. (__asrtgt_d): Likewise. (__lddir_d): Likewise. (__ldpte_d): Likewise. (__crc_w_b_w): Likewise. (__crc_w_h_w): Likewise. (__crc_w_w_w): Likewise. (__crc_w_d_w): Likewise. (__crcc_w_b_w): Likewise. (__crcc_w_h_w): Likewise. (__crcc_w_w_w): Likewise. (__crcc_w_d_w): Likewise. (__csrrd_w): Likewise. (__csrwr_w): Likewise. (__csrxchg_w): Likewise. (__csrrd_d): Likewise. (__csrwr_d): Likewise. (__csrxchg_d): Likewise. (__iocsrrd_b): Likewise. (__iocsrrd_h): Likewise. (__iocsrrd_w): Likewise. (__iocsrrd_d): Likewise. (__iocsrwr_b): Likewise. (__iocsrwr_h): Likewise. (__iocsrwr_w): Likewise. (__iocsrwr_d): Likewise. (__frecipe_s): Likewise. (__frecipe_d): Likewise. (__frsqrte_s): Likewise. (__frsqrte_d): Likewise.
2024-02-18LoongArch: Fix wrong return value type of __iocsrrd_h.Lulu Cheng1-1/+1
gcc/ChangeLog: * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the function return value type to unsigned short.
2024-02-04LoongArch: Fix wrong LSX FP vector negationXi Ruoyao3-27/+18
We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with LSX enabled. Use the vbitrevi.{d/w} instructions to simply reverse the sign bit instead. We are already doing this for LASX and now we can unify them into simd.md. gcc/ChangeLog: * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the incorrect expand. * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr. (elmsgnbit): Likewise. (neg<mode:FVEC>2): New define_insn. * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they are now instantiated in simd.md.
2024-02-04LoongArch: Avoid out-of-bounds access in loongarch_symbol_insnsXi Ruoyao1-1/+2
We call loongarch_symbol_insns with mode = MAX_MACHINE_MODE sometimes. But in loongarch_symbol_insns: if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode)) return 0; And LSX_SUPPORTED_MODE_P is defined as: #define LSX_SUPPORTED_MODE_P(MODE) \ (ISA_HAS_LSX \ && GET_MODE_SIZE (MODE) == UNITS_PER_LSX_REG ... ... GET_MODE_SIZE is expanded to a call to mode_to_bytes, which is defined: ALWAYS_INLINE poly_uint16 mode_to_bytes (machine_mode mode) { #if GCC_VERSION >= 4001 return (__builtin_constant_p (mode) ? mode_size_inline (mode) : mode_size[mode]); #else return mode_size[mode]; #endif } There is an assertion in mode_size_inline: gcc_assert (mode >= 0 && mode < NUM_MACHINE_MODES); Note that NUM_MACHINE_MODES = MAX_MACHINE_MODE (emitted by genmodes.cc), thus if __builtin_constant_p (mode) is evaluated true (it happens when GCC is bootstrapped with LTO+PGO), the assertion will be triggered and cause an ICE. OTOH if __builtin_constant_p (mode) is evaluated false, mode_size[mode] is still an out-of-bound array access (the length or the mode_size array is NUM_MACHINE_MODES). So we shouldn't call LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P with MAX_MACHINE_MODE in loongarch_symbol_insns. This is very similar to a MIPS bug PR98491 fixed by me about 3 years ago. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is MAX_MACHINE_MODE.
2024-02-04LoongArch: testsuite: Fix gcc.dg/vect/vect-reduc-mul_{1, 2}.c FAIL.Li Wei1-55/+163
This FAIL was introduced from r14-6908. The reason is that when merging constant vector permutation implementations, the 128-bit matching situation was not fully considered. In fact, the expansion of 128-bit vectors after merging only supports value-based 4 elements set shuffle, so this time is a complete implementation of the entire 128-bit vector constant permutation, and some structural adjustments have also been made to the code. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust. (loongarch_expand_vselect_vconcat): Ditto. (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement all 128-bit constant permutation situations. (loongarch_expand_lsx_shuffle): Adjust and rename function name. (loongarch_is_imm_set_shuffle): Renamed function name. (loongarch_expand_vec_perm_even_odd): Function forward declaration. (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit extract-even and extract-odd permutations. (loongarch_is_odd_extraction): Delete. (loongarch_is_even_extraction): Ditto. (loongarch_expand_vec_perm_const): Adjust.
2024-02-03LoongArch: Fix an ODR violationXi Ruoyao2-2/+3
When bootstrapping GCC 14 with --with-build-config=bootstrap-lto, an ODR violation is detected: ../../gcc/config/loongarch/loongarch-opts.cc:57: warning: 'abi_minimal_isa' violates the C++ One Definition Rule [-Wodr] 57 | abi_minimal_isa[N_ABI_BASE_TYPES][N_ABI_EXT_TYPES]; ../../gcc/config/loongarch/loongarch-def.cc:186: note: 'abi_minimal_isa' was previously declared here 186 | abi_minimal_isa = array<array<loongarch_isa, N_ABI_EXT_TYPES>, ../../gcc/config/loongarch/loongarch-def.cc:186: note: code may be misoptimized unless '-fno-strict-aliasing' is used Fix it by adding a proper declaration of abi_minimal_isa into loongarch-def.h and remove the ODR-violating local declaration in loongarch-opts.cc. gcc/ChangeLog: * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare. * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove the ODR-violating locale declaration.
2024-02-02LoongArch: Fix incorrect return type for frecipe/frsqrte intrinsic functionsJiahao Xu1-8/+8
gcc/ChangeLog: * config/loongarch/larchintrin.h (__frecipe_s): Update function return type. (__frecipe_d): Ditto. (__frsqrte_s): Ditto. (__frsqrte_d): Ditto. gcc/testsuite/ChangeLog: * gcc.target/loongarch/larch-frecipe-intrinsic.c: New test.
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