| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 5 days | LoongArch: Use normal RTL pattern instead of UNSPEC for {x,}vsr{a,l}ri instru... | Xi Ruoyao | 3 | -44/+29 |
| 5 days | LoongArch: Implement [su]dot_prod* for LSX and LASX modes | Xi Ruoyao | 1 | -0/+29 |
| 5 days | LoongArch: Implement vec_widen_mult_{even,odd}_* for LSX and LASX modes | Xi Ruoyao | 1 | -0/+16 |
| 5 days | LoongArch: Simplify lsx_vpick description | Xi Ruoyao | 2 | -119/+47 |
| 5 days | LoongArch: Simplify {lsx_,lasx_x}vmaddw description | Xi Ruoyao | 4 | -720/+118 |
| 5 days | LoongArch: Simplify {lsx_,lasx_x}vh{add,sub}w description | Xi Ruoyao | 4 | -227/+69 |
| 5 days | LoongArch: Simplify {lsx_,lasx_x}v{add,sub,mul}l{ev,od} description | Xi Ruoyao | 8 | -904/+206 |
| 5 days | LoongArch: Allow moving TImode vectors | Xi Ruoyao | 5 | -78/+45 |
| 5 days | LoongArch: Try harder using vrepli instructions to materialize const vectors | Xi Ruoyao | 3 | -6/+31 |
| 5 days | LoongArch: Accept ADD, IOR or XOR when combining objects with no bits in comm... | Xi Ruoyao | 1 | -19/+27 |
| 10 days | LoongArch: Adjust the cost of ADDRESS_REG_REG. | Lulu Cheng | 7 | -1/+23 |
| 10 days | LoongArch: When -mfpu=none, '__loongarch_frecipe' shouldn't be defined [PR118... | Lulu Cheng | 1 | -12/+15 |
| 10 days | LoongArch: After setting the compilation options, update the predefined macros. | Lulu Cheng | 1 | -0/+14 |
| 10 days | LoongArch: Split the function loongarch_cpu_cpp_builtins into two functions. | Lulu Cheng | 1 | -45/+77 |
| 10 days | LoongArch: Move the function loongarch_register_pragmas to loongarch-c.cc. | Lulu Cheng | 3 | -48/+52 |
| 2025-02-07 | LoongArch: Correct the mode for mask{eq,ne}z | Xi Ruoyao | 1 | -7/+3 |
| 2025-02-06 | LoongArch: Fix ICE caused by illegal calls to builtin functions [PR118561]. | Lulu Cheng | 1 | -2/+5 |
| 2025-01-23 | LoongArch: Fix invalid subregs in xorsign [PR118501] | Xi Ruoyao | 1 | -2/+2 |
| 2025-01-22 | LoongArch: Fix wrong code with <optab>_alsl_reversesi_extended | Xi Ruoyao | 1 | -3/+3 |
| 2025-01-21 | LoongArch: Implement target pragma. | Lulu Cheng | 4 | -7/+76 |
| 2025-01-21 | LoongArch: Implement target attribute. | Lulu Cheng | 4 | -4/+443 |
| 2025-01-20 | LoongArch: Improve reassociation for bitwise operation and left shift [PR 115... | Xi Ruoyao | 3 | -33/+140 |
| 2025-01-20 | LoongArch: Simplify using bstr{ins,pick} instructions for and | Xi Ruoyao | 4 | -48/+53 |
| 2025-01-18 | LoongArch: Fix cost model for alsl | Xi Ruoyao | 1 | -5/+22 |
| 2025-01-18 | LoongArch: Add alsl.wu | Xi Ruoyao | 1 | -4/+4 |
| 2025-01-11 | LoongArch: Generate the final immediate for lu12i.w, lu32i.d and lu52i.d | mengqinggang | 5 | -19/+35 |
| 2025-01-10 | LoongArch: Opitmize the cost of vec_construct. | chenxiaolong | 1 | -3/+3 |
| 2025-01-07 | LoongArch: Optimize initializing fp resgister to zero | Deng Jianbo | 1 | -0/+2 |
| 2025-01-02 | Update copyright years. | Jakub Jelinek | 1 | -3/+3 |
| 2025-01-02 | Update copyright years. | Jakub Jelinek | 45 | -46/+46 |
| 2025-01-02 | LoongArch: Optimize for conditional move operations | Guo Jie | 1 | -1/+102 |
| 2025-01-02 | LoongArch: Add standard patterns uabd and sabd | Guo Jie | 4 | -57/+48 |
| 2025-01-02 | LoongArch: Add some vector pack/unpack patterns | Guo Jie | 5 | -135/+198 |
| 2025-01-02 | LoongArch: Adjust insn patterns for better combine | Guo Jie | 1 | -6/+17 |
| 2025-01-02 | LoongArch: Fix bugs in insn patterns lasx_xvrepl128vei_b/h/w/d_internal | Guo Jie | 2 | -42/+38 |
| 2025-01-02 | LoongArch: Fix selector error in lasx_xvexth_h/w/d* patterns | Guo Jie | 1 | -7/+7 |
| 2025-01-02 | LoongArch: Remove useless UNSPECs and define_mode_attrs | Guo Jie | 2 | -101/+0 |
| 2024-12-31 | LoongArch: Implement vector cbranch optab for LSX and LASX | Jiahao Xu | 1 | -0/+30 |
| 2024-12-27 | LoongArch: Support immediate_operand for vec_cmp | Jiahao Xu | 4 | -50/+52 |
| 2024-12-25 | LoongArch: Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook | Jiahao Xu | 1 | -0/+38 |
| 2024-12-18 | LoongArch: Combine xor and crc instructions | Xi Ruoyao | 1 | -0/+25 |
| 2024-12-18 | LoongArch: Add CRC expander to generate faster CRC | Xi Ruoyao | 1 | -0/+57 |
| 2024-12-18 | LoongArch: Add bit reverse operations | Xi Ruoyao | 1 | -0/+51 |
| 2024-12-18 | LoongArch: Remove QHSD and use QHWD instead | Xi Ruoyao | 1 | -3/+2 |
| 2024-11-30 | LoongArch: Mask shift offset when emit {xv, v}{srl, sll, sra} with sameimm ve... | Jinyang He | 5 | -37/+110 |
| 2024-11-29 | __builtin_prefetch fixes [PR117608] | Jakub Jelinek | 1 | -1/+2 |
| 2024-11-22 | build: Remove INCLUDE_MEMORY [PR117737] | Andrew Pinski | 2 | -2/+0 |
| 2024-11-22 | LoongArch: Remove redundant code. | Lulu Cheng | 3 | -111/+0 |
| 2024-11-22 | LoongArch: Fix clerical errors in lasx_xvreplgr2vr_* and lsx_vreplgr2vr_*. | Lulu Cheng | 2 | -2/+2 |
| 2024-11-22 | LoongArch: Make __builtin_lsx_vorn_v and __builtin_lasx_xvorn_v arguments and... | Xi Ruoyao | 3 | -6/+6 |
