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| author | Lulu Cheng <chenglulu@loongson.cn> | 2024-08-08 09:59:28 +0800 |
|---|---|---|
| committer | Lulu Cheng <chenglulu@loongson.cn> | 2024-08-12 09:33:04 +0800 |
| commit | 7bf4cd48d4494ba65680578e9c7ae9a1b809aeaf (patch) | |
| tree | 822358fb63f8565aecd80a5785c3de0e75fff62f /gcc/config/loongarch | |
| parent | 0498f8bda1d08b8ed8100d759917792baf2da15f (diff) | |
| download | gcc-7bf4cd48d4494ba65680578e9c7ae9a1b809aeaf.zip gcc-7bf4cd48d4494ba65680578e9c7ae9a1b809aeaf.tar.gz gcc-7bf4cd48d4494ba65680578e9c7ae9a1b809aeaf.tar.bz2 | |
LoongArch: Provide ashr lshr and ashl RTL pattern for vectors.
We support vashr vlshr and vashl. However, in r15-1638 support optimize
x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31.
To support this optimization, vector ashr lshr and ashl need to be implemented.
gcc/ChangeLog:
* config/loongarch/loongarch.md (insn): Added rotatert rotr pairs.
* config/loongarch/simd.md (rotr<mode>3): Remove to ...
(<optab><mode>3): This.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/vect-ashr-lshr.C: New test.
Diffstat (limited to 'gcc/config/loongarch')
| -rw-r--r-- | gcc/config/loongarch/loongarch.md | 1 | ||||
| -rw-r--r-- | gcc/config/loongarch/simd.md | 13 |
2 files changed, 8 insertions, 6 deletions
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 261cb7d..73cdb38 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -559,6 +559,7 @@ (define_code_attr insn [(ashift "sll") (ashiftrt "sra") (lshiftrt "srl") + (rotatert "rotr") (ior "or") (xor "xor") (and "and") diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 00ff282..45ea114 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -306,14 +306,15 @@ operands[4] = gen_reg_rtx (<MODE>mode); }); -;; <x>vrotri.{b/h/w/d} +;; <x>v{rotr/sll/sra/srl}i.{b/h/w/d} -(define_insn "rotr<mode>3" +(define_insn "<optab><mode>3" [(set (match_operand:IVEC 0 "register_operand" "=f") - (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") - (match_operand:SI 2 "const_<bitimm>_operand")))] - "" - "<x>vrotri.<simdfmt>\t%<wu>0,%<wu>1,%2"; + (shift_w:IVEC + (match_operand:IVEC 1 "register_operand" "f") + (match_operand:SI 2 "const_<bitimm>_operand")))] + "ISA_HAS_LSX" + "<x>v<insn>i.<simdfmt>\t%<wu>0,%<wu>1,%2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "<MODE>")]) |