Age | Commit message (Expand) | Author | Files | Lines |
2022-03-16 | RISC-V: Add version info for zk, zkn and zks | Kito Cheng | 1 | -0/+4 |
2022-03-16 | RISC-V: Handle combine extension in canonical ordering. | LiaoShihua | 1 | -0/+56 |
2022-03-04 | rs6000: Allow -mlong-double-64 after -mabi={ibm,ieee}longdouble [PR104208, PR... | Peter Bergner | 1 | -0/+10 |
2022-02-09 | i386: -mno-xsave should disable all relevant ISA flags [PR104462] | Uros Bizjak | 1 | -1/+2 |
2022-01-24 | properly disable -fsplit-stack on non-glibc targets [PR104170] | Jakub Jelinek | 2 | -4/+6 |
2022-01-24 | RISC-V: Do not emit zcisr and zifencei if i-ext is 2.0 | Kito Cheng | 1 | -2/+12 |
2022-01-21 | x86: Properly disable -fsplit-stack support on non-glibc targets | H.J. Lu | 1 | -6/+11 |
2022-01-21 | Disable -fsplit-stack support on non-glibc targets | Sören Tempel | 1 | -4/+10 |
2022-01-18 | RISC-V: Fix use-after-free error in `parse_multiletter_ext' | Maciej W. Rozycki | 1 | -1/+1 |
2022-01-18 | riscv: fix -Wformat-diag errors. | Martin Liska | 1 | -8/+8 |
2022-01-17 | Change references of .c files to .cc files | Martin Liska | 4 | -5/+5 |
2022-01-17 | Rename .c files to .cc files. | Martin Liska | 50 | -0/+0 |
2022-01-14 | ARM: fix -Wformat= error | Martin Liska | 1 | -1/+1 |
2022-01-13 | Fix -Wformat-diag for ARM target. | Martin Liska | 1 | -6/+6 |
2022-01-07 | RISC-V: Minimal support of vector extensions | Kito Cheng | 1 | -0/+86 |
2022-01-07 | RISC-V: Allow extension name contain digit | Kito Cheng | 1 | -4/+38 |
2022-01-04 | x86: Update model value for Alderlake and Rocketlake | Cui,Lili | 1 | -0/+2 |
2022-01-03 | Update copyright years. | Jakub Jelinek | 57 | -57/+57 |
2021-12-04 | RISC-V: Add implied defines of Zk, Zkn and Zks | SiYu Wu | 1 | -1/+15 |
2021-12-04 | RISC-V: Add option defines for Scalar Cryptography | SiYu Wu | 1 | -0/+22 |
2021-11-11 | RISC-V: Fix wrong zifencei handling in riscv_subset_list::to_string | Kito Cheng | 1 | -1/+1 |
2021-11-10 | [PR/target 102957] Allow Z*-ext extension with only 2 char. | Kito Cheng | 1 | -1/+0 |
2021-10-25 | RISC-V: Minimal support of bitmanip extension | Kito Cheng | 1 | -0/+10 |
2021-10-05 | Mark argument as unused | Jan-Benedict Glaw | 1 | -1/+2 |
2021-09-21 | arm: pass architecture extensions to assembler if supported | Richard Earnshaw | 1 | -0/+10 |
2021-09-17 | x86: Update -mtune=tremont | H.J. Lu | 1 | -1/+1 |
2021-09-13 | i386: support micro-levels in target{,_clone} attrs [PR101696] | Martin Liska | 3 | -0/+61 |
2021-09-08 | AVX512FP16: Initial support for AVX512FP16 feature and scalar _Float16 instru... | Guo, Xuepeng | 4 | -2/+28 |
2021-08-12 | arc: Small data doesn't need fcommon option | Claudiu Zissulescu | 1 | -3/+1 |
2021-07-18 | x86: Enable the GPR only instructions for -mgeneral-regs-only | H.J. Lu | 1 | -2/+25 |
2021-06-30 | [amdgcn] Use frame pointer for CFA expressions. | Hafiz Abid Qadeer | 1 | -1/+1 |
2021-06-18 | arm: Fix multilib mapping for CDE extensions [PR100856]. | Srinath Parvathaneni | 1 | -6/+41 |
2021-06-07 | Reformat target.def for better parsing. | Martin Liska | 1 | -16/+16 |
2021-06-03 | arc: Remove obsolete options | Claudiu Zissulescu | 1 | -1/+0 |
2021-05-19 | RISC-V: Properly parse the letter 'p' in '-march'. | Geng Qi | 1 | -33/+35 |
2021-05-18 | Use startswith in targets. | Martin Liska | 3 | -4/+4 |
2021-05-10 | arc: Fix compilation warnings. | Claudiu Zissulescu | 1 | -1/+1 |
2021-04-27 | Synchronize Rocket Lake's processor_names and processor_cost_table with proce... | Cui,Lili | 1 | -1/+1 |
2021-04-21 | x86: Add -mmwait for -mgeneral-regs-only | H.J. Lu | 1 | -0/+15 |
2021-04-12 | Add rocketlake to gcc. | Cui,Lili | 3 | -2/+13 |
2021-04-12 | Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2 | Cui,Lili | 1 | -0/+1 |
2021-03-24 | i386: fix -march=amd crash | Martin Liska | 1 | -1/+1 |
2021-03-23 | RISC-V: Add riscv{32,64}be with big endian as default | Marcus Comstedt | 1 | -0/+5 |
2021-03-09 | arm: fix bootstrap failure following automatic mode selection patch | Richard Earnshaw | 1 | -1/+1 |
2021-03-03 | arm: Ignore --with-mode when CPU only supports one instruction set. | Richard Earnshaw | 1 | -6/+43 |
2021-03-02 | IBM Z: arch14: Add command line options | Andreas Krebbel | 1 | -0/+4 |
2021-01-28 | RISC-V: Fix -march option parsing when extension exists. | Xing GUO | 1 | -3/+1 |
2021-01-14 | i386: Resolve variable shadowing in i386-options.c [PR98671] | Uros Bizjak | 1 | -1/+1 |
2021-01-08 | RISC-V: Implement new style of architecture extension test macros. | Kito Cheng | 1 | -0/+5 |
2021-01-08 | RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h | Kito Cheng | 1 | -66/+1 |